Xilinx Virtex-6 FPGA Getting Started Manual page 74

Getting Started with the Virtex-6 FPGA IBERT Reference Design
15. Configure the bit error ratio test (BERT) parameter settings (see
X-Ref Target - Figure 78
16. View the reported BERT (see
X-Ref Target - Figure 79
Congratulations! The IBERT reference design for the Virtex-6 FPGA Connectivity Kit has
been set up and the pre-built demo that uses the GTX transceivers running at 3.125 Gb/s
has been tested.
For further details on other example reference designs available for the ML605 board, refer
to
74
a. Set the TX/RX data patterns to PRBS 7-bit and 15-bit.
b. Click the BERT Reset buttons for each channel.
Figure 78: Configuring the BERT Settings for the GTX Transceiver Channels
Figure 79: Verify the Bit Error Ratio on All Four Transceiver Channels
http://www.xilinx.com/ml605
www.xilinx.com
Figure 79). The RX bit error count should be 0.
and click on ML605 Documentation.
Virtex-6 FPGA Connectivity Kit Getting Started
Figure 78):
UG664_55_021810
UG664_56_021810
UG664 (v1.4) July 6, 2011