Xilinx Virtex-6 FPGA Getting Started Manual page 72

Getting Started with the Virtex-6 FPGA IBERT Reference Design
11. Load the ChipScope Pro Analyzer project:
X-Ref Target - Figure 74
12. Load and reset the IBERT reference design through the GUI (see
X-Ref Target - Figure 75
72
a. Click Yes on the dialog box shown in
Figure 74: Load the ChipScope Tool Project and Communicate with the IBERT
GTX0_113  FMC Daughter Card connector: DP3 SATA2 Host Channel
GTX1_113  FMC Daughter Card connector: DP2 SATA1 Host Channel
GTX2_113  FMC Daughter Card connector: DP1 SMA Channel
GTX3_113  FMC Daughter Card connector: DP0 SMA Channel
Figure 75: Load and Reset the IBERT Reference Design
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Figure 74.
Reference Design
Virtex-6 FPGA Connectivity Kit Getting Started
UG664_51_011710
Figure 75).
UG664_52_021810
UG664 (v1.4) July 6, 2011