Xilinx Virtex-6 FPGA Getting Started Manual page 67

X-Ref Target - Figure 66
X-Ref Target - Figure 67
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Virtex-6 FPGA IBERT Reference Design
b. Connect J6 to J8 (see
Figure 66: Configuring the SMA Transceiver Channel with External Loopback - II
c. Connect J3 to J9 (see
Figure 67: Configuring the SMA Transceiver Channel with External Loopback - III
www.xilinx.com
Figure 66).
Figure 67).
UG664_43_021810
UG664_44_021810
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