Xilinx Virtex-6 FPGA Getting Started Manual page 68

Getting Started with the Virtex-6 FPGA IBERT Reference Design
X-Ref Target - Figure 68
X-Ref Target - Figure 69
68
d. Connect J5 to J7 (see
Figure 68: Configuring the SMA Transceiver Channel with External Loopback - IV
e. Connect J11 to J12 with a SATA loopback cable included in the Virtex-6 FPGA
Connectivity Kit (see
Figure 69: Configuring the SMA Transceiver Channels and SATA Channels with
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Figure 68).
Figure 69).
External Loopback - V
Virtex-6 FPGA Connectivity Kit Getting Started
UG664_45_011610
UG664_46_011610
UG664 (v1.4) July 6, 2011