Modifying The Virtex-6 Fpga Targeted Reference Design; Hardware Modifications - Xilinx Virtex-6 FPGA Getting Started Manual

Modifying the Virtex-6 FPGA Targeted Reference Design

Modifying the Virtex-6 FPGA Targeted Reference Design
This section describes how to modify the design:
•
•

Hardware Modifications

This section describes how the hardware is modified. This exercise modifies the PCI
Express vendor ID.
To make RTL design changes and implement the design, follow these steps:
1.
2.
3.
4.
5.
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Hardware modifications
Note:
Before running any command line scripts, refer to the "Platform Specific Instructions"
section in UG631, ISE Design Suite: Installation, Licensing, and Release Notes
(http://www.xilinx.com/support/documentation) to learn how to set the appropriate environment
variables for the operating system. All scripts mentioned in this document assume the XILINX
environment variables are set.
Software modifications
Use the PC system or laptop on which the Xilinx design tools were installed.
Copy the contents of the included USB stick into a local directory on this machine.
Make design changes:
a. Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi/design/source/
directory.
b. Edit the v6_pcie_10Gdma_ddr3_xaui.v file.
c. Search for this string: VENDOR_ID.
d. Change the alphanumeric value 10EE on this line to the vendor ID assigned to the
user's company by PCI-SIG (e.g., the vendor ID for Xilinx is 10EE). Change this
value to 19AA.
e. Save changes and exit.
Generate the MIG IP core required for the Targeted Reference Design:
a. Open a command or a terminal window.
b. Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi/design/ip_cores/mig
directory.
c. Execute this command at the command prompt:
$ coregen -b mig.xco -p coregen.cgp
Wait for this command to complete before proceeding.
Build and implement the design:
a. Open a terminal window.
b. Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi/design/implement/
directory.
c. Follow the implementation flow steps depending on the operating system:
- For Linux: Execute this command on the command line:
$ source implement.sh x4 gen2
- For Windows: Execute this command on the command line:
$ implement.bat -lanemode x4gen2
www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011