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Xilinx MultiLINX Series Hardware User's Manual

Xilinx MultiLINX Series Hardware User's Manual

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Hardware User
Guide
Hardware User Guide — Alliance 3.1i
Cable Hardware
™
MutliLINX
FPGA Design Demonstra-
tion Board
CPLD Design Demonstra-
tion Board
Glossary
Cable
Printed in U.S.A.

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Summary of Contents for Xilinx MultiLINX Series

  • Page 1 Hardware User Cable Hardware ™ Guide MutliLINX Cable FPGA Design Demonstra- tion Board CPLD Design Demonstra- tion Board Glossary Hardware User Guide — Alliance 3.1i Printed in U.S.A.
  • Page 2 Hardware User Guide...
  • Page 3 All other trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others.
  • Page 4 Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

  • Page 5: Manual Contents

    CPLD Design Demonstration board for design verification Before using this manual, you should be familiar with the operations that are common to all Xilinx software tools: how to bring up the system, select a tool for use, specify operations, and manage design data.

  • Page 6: Additional Resources

    Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm Xcell Journals Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm Technical Tips Latest news, design tips, and patch information for the Xilinx design environment http://support.xilinx.com/support/techsup/journals/ index.htm Xilinx Development System...

  • Page 7: Conventions

    Conventions This manual uses the following conventions. An example illustrates each convention. Typographical The following conventions are used for all documents. • Courier font indicates messages, prompts, and program files that the system displays. speed grade: - 100 • Courier bold indicates literal commands that you enter in a syntactical statement.

  • Page 8: Online Document

    Online Document The following conventions are used for online documents. • Red-underlined text indicates an interbook link, which is a cross- reference to another book. Click the red-underlined text to open the specified cross-reference. Xilinx Development System...
  • Page 9 • Blue-underlined text indicates an intrabook link, which is a cross- reference within a book. Click the blue-underlined text to open the specified cross-reference. Hardware User Guide...
  • Page 10 Hardware User Guide Xilinx Development System...

  • Page 11: Table Of Contents

    Contents About This Manual Manual Contents ................i Additional Resources ..............ii Conventions Typographical................. iii Online Document ................iv Chapter 1 Cable Hardware Cable Overview................1-1 Selecting a Cable..............1-1 MultiLINX Cable..............1-1 Parallel Cable ..............1-2 XChecker Cable..............1-2 Software Support ..............
  • Page 12 Download Cable Support ............3-2 Software Support ..............3-2 Board Features ................. 3-2 General Components ..............3-4 +5 V Power Connector (J9) ............3-5 Unregulated Power Input (J12) ..........3-6 +5 V Regulator Option (U3) ............3-6 viii Xilinx Development System...
  • Page 13 Contents RESET Pushbutton (SW4)............3-7 SPARE Pushbutton (SW5) ............3-7 PROG Pushbutton (SW6) ............3-7 Eight General-Purpose Input Switches (SW3)......3-7 Seven-Segment Displays (U6, U7, U8) ........3-9 LED Indicators (D1-D8, D9-D16) ..........3-10 I/O Line Connections ..............3-11 Optional Crystal Oscillator (Y1)..........3-11 Prototype Area ................
  • Page 14 Printed Circuit Board (PCB) ............4-2 Prototyping Area ............... 4-2 Power Supply................4-2 Demonstration Board Schematics..........4-3 Foundation Design Tutorial ............4-5 Example I: Schematic Design Entry.......... 4-5 Schematic With VHDL Macro Design ........4-6 Example 2: VHDL Design Entry..........4-7 Xilinx Development System...

  • Page 15: Chapter 1 Cable Hardware

    • “Download Cable Schematic” Cable Overview There are three cables available for use with Xilinx Alliance and Foundation software. The MultiLINX Cable supports USB and RS- 232 serial port connections, the Parallel Cable III supports parallel port, and the XChecker Cable supports RS-232 serial ports.

  • Page 16: Parallel Cable

    Universal Serial Bus (USB) port or an RS-232 interface. The additional flying wires support the various configuration modes available on Xilinx configuration cables. Parallel Cable The Parallel Cable III connects to the parallel printer port of a PC.

  • Page 17: Cable Limitations

    Virtex family. Note Debug is not available with the MultiLINX Cable when using the Hardware Debugger Software in the 2.1i Xilinx release version. XChecker Hardware Drawbacks Following are the limitations of the XChecker cable.

  • Page 18: Previous Cable Versions

    Hardware User Guide • Works at multiple supply voltages (5 V, 3.3 V, and 2.5 V). • Supports JTAG configuration for all Xilinx devices. • Supports SelectMAP configuration mode for Virtex. Previous Cable Versions This section details considerations for using previous download cables with the Hardware Debugger Software.

  • Page 19: Cable Baud Rates

    9600, 19200, and 38400 and 115200 MultiLINX Cable and Flying Leads The MultiLINX Cable is a device for configuring and verifying Xilinx FPGAs and CPLDs. The MultiLINX Cable is shipped with four sets of flying lead wires. A USB Cable and RS-232 Cable (with adapter) are also supplied.
  • Page 20 Flying Lead Connector Set #3 MultiLINX Flying Lead Connector Set #4 CS0(CS) CLK2-IN CLK2-OUT RS(RDWR) RDY/BUSY X8926 Figure 1-1 MultiLINX Cable and Flying Lead Connectors The following figure shows the top and bottom view of the Multi- LINX Cable. Xilinx Development System...

  • Page 21: External Power For The Multilinx Cable

    Flying Wire Set #1 are connected to the VCC (red wire) and Ground (black wire) lines of the circuit board that is powering the Xilinx device. The external power for the MultiLINX Cable is shown in the following figure.

  • Page 22: Parallel Cable Iii

    The Parallel Cable III is a cable assembly which contains a buffer to protect your PC’s parallel port and a set of headers to connect to your target system. The cable can be used with a single CPLD or FPGA device, or several devices connected in a daisy chain. Xilinx Development System...

  • Page 23: Flying Leads

    Cable Hardware The transmission speed of the this cable is determined solely by the speed at which the host PC can transmit data through its parallel port interface. Using the Parallel Cable III requires a PC equipped with an AT compatible parallel port interface and a DB25 standard printer connector.
  • Page 24 Connections to CCLK Target System PROG X8325 Figure 1-4 Parallel Cable III and FPGA Flying Leads The following figure shows top and bottom views of the Parallel Cable III, including the FPGA and JTAG (CPLD) headers. 1-10 Xilinx Development System...

  • Page 25: Configuring Cplds With The Parallel Cable Iii

    Cable Hardware Parallel Cable III Top View JTAG Header Parallel Cable III CAUTION CCLK Model DLC5 Power 5V 10mA Typ. Serial JT - 1 2 3 4 5 SENSITIVE PROG ELECTRONIC Made in U.S.A DEVICE Bottom View X7252 Figure 1-5 Parallel Cable III Note The plastic cover of the Parallel Cable III is grey, while the XChecker Cable is beige.
  • Page 26 Test Clock – Drives the test Connect to system TCK logic for all devices on a pin. JTAG chain. Test Data Output – data Connect to system from the target system is TDO pin. read at this pin. 1-12 Xilinx Development System...

  • Page 27: Configuring Fpgas With The Parallel Cable Iii

    Note TRST is an optional pin in the JTAG (IEEE 1149.1) specification, and is not used by XC9500 CPLDs. If any of your non-Xilinx parts have a TRST pin, the pin should be connected to VCC Configuring FPGAs With the Parallel Cable III This section details the connections needed to configure FPGAs with the Parallel Cable III.
  • Page 28 Target System X8327 Figure 1-8 Parallel Cable III Connections to XC3000 Device Note If you are using the Xilinx FPGA Demonstration Board, see the “Mode Switch Settings” section of the “FPGA Design Demonstration Board” chapter for specific configuration information. 1-14...
  • Page 29 Cable Hardware XChecker Cable The XChecker hardware consists of a cable assembly with internal logic, a test fixture, and a set of headers to connect the cable to your target system. The cable can be used with a single FPGA or CPLD, or several devices connected in a daisy chain.
  • Page 30 CCLK Target System PROG INIT Flying Lead Connector 2 TRIG Connections to Target System CLK1 CLK0 X8322 Figure 1-9 XChecker Cable and Flying Leads The following figure shows top and bottom views of the XChecker Cable. 1-16 Xilinx Development System...

  • Page 31: Xchecker Cable

    Cable Hardware XChecker Cable Top View Header 2 Header 1 Model : DLC4 CAUTION TRIG Power : 5V 100mA Typ. CCLK Serial: DL - 1 2 3 4 5 PROG SENSITIVE CLKI INIT ELECTRONIC Made in U.S.A CLKO DEVICE Bottom View X7249 Figure 1-10 XChecker Cable Note The plastic cover of the XChecker Cable is beige, while the...

  • Page 32: Xchecker Baud Rates

    Note TRST is an optional pin in the JTAG (IEEE 1149.1) specification, and is not used by XC9500 CPLDs (If any of your non-Xilinx parts have a TRST pin, the pin should be connected to VCC). Once installed properly, the connectors provide power to the cable and allow download and readback of configuration data.

  • Page 33: Configuring Fpgas With The Xchecker Cable

    This section details the connections needed to configure FPGAs with the XChecker Cable. Note If you are using the Xilinx FPGA Design Demonstration Board, see the “Demonstration Board Operation” section of the “FPGA Design Demonstration Board” chapter for specific configuration information.

  • Page 34: Pin Connection Considerations

    XC3000 FPGA in Slave Serial Mode Not Used XChecker with Header 1 Target System X8324 Figure 1-12 XChecker Connections to XC3000 Device Pin Connection Considerations The following adjustments will make the process of connecting and downloading easier. 1-20 Xilinx Development System...

  • Page 35: Cable Connection Procedure

    Start the appropriate Xilinx software package and configure your device. The JTAG Programmer Software and Hardware Debugger Software will automatically identify the download cables when correctly connected.

  • Page 36: Setting Up The Cable

    Download Cable Schematic The following figure is an internal schematic of the Parallel Cable III. You must use the recommended lengths for parallel cables. Xilinx cables are typically six feet (approximately two meters) in length between the connector and active circuitry. Keep the wires between the headers and target system as short as possible.
  • Page 37 Cable Hardware JTAG Header 1N5817 1N5817 VCC SENSE .01uF DONE 5.1K 100pF PROG 100pF TMS_IN 100pF CTRL CCLK 100pF U1 = 74HC125 U2 = 74HC125 BUSY PROG SHIELD DB25 MALE Serial JT -05000 and above FPGA Header CONNECTOR for EPP parallel ports. X7557 Figure 1-13 Parallel Cable III Schematic Hardware User Guide...
  • Page 38 Hardware User Guide 1-24 Xilinx Development System...

  • Page 39: Chapter 2 Mutlilinx ™ Cable

    Cable is the next generation configuration and readback tool for FPGA’s and CPLD’s. During the integration of Xilinx programmable logic into your design, the MultiLINX Cable can be used to troubleshoot your configuration setup, and diagnose configuration problems associated with Xilinx programmable logic.

  • Page 40: Multilinx Platform Support

    X indicates applicable ports that can be used with the MultiLINX Cable on spec- ified platforms. MultiLINX Flying Wires The MultiLINX Cable is shipped with four sets of flying lead wires. The following figure shows these four sets of MultiLINX flying lead connectors. Xilinx Development System...
  • Page 41 ™ MutliLINX Cable MultiLINX Flying Lead Connector Set #1 CCLK DONE(D/P) PROG INIT MultiLINX Flying Lead Connector Set #2 RD(TDO) TRIG CLK1-IN CLK1-OUT MultiLINX Flying Lead Connector Set #3 MultiLINX Flying Lead Connector Set #4 CS0(CS) CLK2-IN CLK2-OUT RS(RDWR) RDY/BUSY X8919 Figure 2-1 MultiLINX Flying Wires The MultiLINX Flying wires are described in the following table.
  • Page 42 Active Low signal to initiate the configuration process. INIT Initialize — Initialization sequencing pin during configu- ration (Indicates start of configu- ration). A logical zero on this pin during configuration indicates a data error. Xilinx Development System...
  • Page 43 ™ MutliLINX Cable Table 2-2 MultiLINX Pin Descriptions Signal Name Function Reset —Pin used to reset internal FPGA logic. Connection to this pin is optional during configura- tion. During configuration, a Low pulse causes XC3000A devices to restart configuration. After configuration, this pin can drive Low to reset target FPGA internal latches and flip-flops.
  • Page 44 Chip Select — CS on the Virtex; and CS0 on the XC4000 and XC5200 FPGAs. The CS0/CS pin represents a chip select to the Chip Select — The CS1 pin repre- sents Chip Select to the XC4000 and XC5200 FPGAs during configuration. Xilinx Development System...
  • Page 45 ™ MutliLINX Cable Table 2-2 MultiLINX Pin Descriptions Signal Name Function Chip Select — The CS2 pin repre- sents Chip Select to the XC3000 FPGA while using the Peripheral configuration mode. CLK2-IN Clock Input — Transmits your system clock to the MultiLINX electronics.

  • Page 46: Multilinx Baud Rates

    The red (PWR) and black (GND) wires from Flying Wire Set #1 are connected to the VCC (red wire) and Ground (black wire) lines of the circuit board that is powering the Xilinx device. The minimum input voltage to the cable is 2.5 V (.8 A). The maximum input voltage is 5 V (.4 A).
  • Page 47 300 mA at 2.5 V. Note The voltage supplied to the MultiLINX Cable does not need to be the same voltage powering the Xilinx device. The cable generates its own voltages from the power supplied to it.

  • Page 48: Device Configuration Modes

    This section details the connections needed to download configura- tion data with the MultiLINX Cable. Slave Serial Mode (XC3000) The following figure shows in detail the Slave Serial Mode connec- tions to a XC3000 device for Downloading Configuration Data. 2-10 Xilinx Development System...
  • Page 49 CLK2-OUT DONE (D / P) RS (RDWR) PROG CLK1-IN INIT RDY/BUSY CLK1-OUT Circuit Board XILINX device PWRDN RESET INIT CCLK NOTE: Pull-up resistors are 4.7k ohm. X8942 Figure 2-3 Slave Serial Mode (XC3000) Slave Serial Mode (Virtex, Spartan, XC5200, XC4000) The following figure shows in detail the Slave Serial Mode connec- tions for Virtex, Spartan, XC5200, and XC4000 devices.

  • Page 50: Downloading Configuration Data Or Verification Of Data

    This section details the connections needed for downloading configu- ration data or the verification of data with the MultiLINX Cable. SelectMAP Mode (Virtex) The following figure shows in detail the SelectMAP Mode connec- tions for Virtex devices. 2-12 Xilinx Development System...

  • Page 51: Downloading Configuration Data

    Vcco BUSY/DOUT INIT PROG WRITE DONE CCLK XILINX device Vcco Vcco NOTE: Pull-up resistors are 4.7k ohm. X8940 Figure 2-5 SelectMAP Mode (Virtex) Downloading Configuration Data This section details the connections needed for downloading configu- ration data with the MultiLINX Cable in JTAG Mode.

  • Page 52: Downloading/Verification Of Configuration Data

    This section details the connections needed for downloading/verifi- cation of configuration data with the MultiLINX Cable in Slave Serial Mode. Slave Serial Mode (XC3000) The following figure shows in detail the Slave Serial Mode connec- tions for the XC3000 device. 2-14 Xilinx Development System...

  • Page 53: Slave Serial Mode (Spartan, Xc5200, Xc4000)

    CLK2-IN CCLK CLK2-OUT DONE (D / P) RS (RDWR) PROG CLK1-IN INIT RDY/BUSY CLK1-OUT Circuit Board XILINX device PWRDN RESET INIT System Clock (x) GCK (x) CCLK System Clock (y) GCK (y) (optional) NOTE: Pull-up resistors are 4.7k ohm. X8938...

  • Page 54: Selectmap Mode (Virtex)

    NOTE: Pull-up resistors are 4.7k ohm. X8937 Figure 2-8 Slave Serial Mode (Spartan, XC5200, XC4000) SelectMAP Mode (Virtex) The following figure shows in detail the SelectMAP Mode connec- tions for downloading/verification of configuration data with Virtex devices. 2-16 Xilinx Development System...

  • Page 55: Selectmap Mode (Virtex With Asynchronous Probing)

    TRIG CLK2-IN CCLK CLK2-OUT DONE (D / P) RS (RDWR) PROG CLK1-IN INIT RDY/BUSY CLK1-OUT (optional) Circuit Board Vcco XILINX device BUSY/DOUT INIT PROG WRITE DONE GCK (x) System Clock (x) CCLK System Clock (y) GCK (y) (optional) Vcco Vcco NOTE: Pull-up resistors are 4.7k ohm.

  • Page 56: Jtag Mode (Xc9000, Virtex, Spartan, Xc5200, Xc4000)

    NOTE: Pull-up resistors are 4.7k ohm. X8935 Figure 2-10 SelectMAP Mode (Virtex with Asynchronous Probing) JTAG Mode (XC9000, Virtex, Spartan, XC5200, XC4000) The following figure shows in detail the JTAG Mode connections for XC9000, Virtex, Spartan, XC5200, and XC4000 devices. 2-18 Xilinx Development System...

  • Page 57: Verification Of Configuration Data Only

    DONE (D / P) RS (RDWR) PROG CLK1-IN INIT RDY/BUSY CLK1-OUT Circuit Board System Clock (x) XILINX device GCK (x) INIT (optional) User I/O: TRIGGER PROG GCK (y) (optional) System Clock (y) see data sheet of the device (if applicable) NOTE: Pull-up resistors are 4.7k ohm.
  • Page 58 CCLK X8933 Figure 2-12 Verification of Configuration Data Only (Spartan, XC5200, XC4000) Verification of Configuration Data Only (XC3000) The following figure shows in detail the connections for verification of configuration data only with the XC3000 device. 2-20 Xilinx Development System...

  • Page 59: Synchronous Probing

    RS (RDWR) PROG CLK1-IN INIT RDY/BUSY CLK1-OUT Circuit Board XILINX device CCLK X8932 Figure 2-13 Verification of Configuration Data Only (XC3000) Synchronous Probing This section details the connections needed for synchronous probing using the MultiLINX Cable. Slave Serial Mode (XC3000) The following figure shows in detail the Slave Serial Mode connec- tions for synchronous probing using the XC3000 device.
  • Page 60 XILINX device CCLK X8932 Figure 2-14 Slave Serial Mode (XC3000) Slave Serial Mode (Spartan, XC5200, XC4000) The following figure shows in detail the Slave Serial Mode connec- tions for synchronous probing using Spartan, XC5200, and XC4000 devices. 2-22 Xilinx Development System...
  • Page 61 CCLK CLK2-OUT DONE (D / P) RS (RDWR) PROG CLK1-IN INIT RDY/BUSY CLK1-OUT Circuit Board System Clock (x) XILINX device User I/O: RESET INIT PROG DONE CCLK (optional) GCK (y) System Clock (y) NOTE: Pull-up resistors are 4.7k ohm. X8929...
  • Page 62 CAPTURE Capture Control Logic CCLK CAPCLK (optional) GCK (y) Vcco System Clock (y) Vcco NOTE: Pull-up resistors are 4.7k ohm. X8930 Figure 2-16 SelectMAP Mode (Virtex) JTAG Mode In JTAG mode Synchronous Probing is not available. 2-24 Xilinx Development System...

  • Page 63: Chapter 3 Fpga Design Demonstration Board

    Xilinx FPGA architecture. The FPGA Demonstration Board allows you to become familiar with some of the Xilinx FPGA device families and the Xilinx software development system. This chapter contains the following sections.

  • Page 64: Download Cable Support

    • Spartan™ Product Families Note: The Spartan series is a low-cost FPGA family, based on the XC4000 devices. See the Xilinx web site or the 1998 Xilinx Databook for more information about Spartan. Download Cable Support The FPGA Demonstration Board is shipped with two short "ribbon"...
  • Page 65 FPGA Design Demonstration Board • Total of three 8-pin DIP switches to set up the XC4000 and XC3000 FPGAs, as shown in the following table. Table 3-1 DIP Switch Configuration XC3000 SW1 XC4000 SW2 Switch MPE (multiple configurations) SPE (single configuration) MCLK DOUT INIT...

  • Page 66: General Components

    X4710 Bars Figure 3-1 FPGA Demonstration Board Displays General Components This section describes the common components that are found on the FPGA Demonstration Board. The following figure shows the compo- nent layout of the FPGA Demonstration Board. Xilinx Development System...

  • Page 67: Power Connector (J9)

    FPGA Design Demonstration Board X4689 Figure 3-2 FPGA Demonstration Board +5 V Power Connector (J9) A regulated +5 volts and ground connected to the FPGA Demonstra- tion Board through connector J9. Pin 1 (square pad) is +5 V and pin 2 Hardware User Guide...

  • Page 68: Unregulated Power Input (J12)

    Pin 1 (square pad) is Vin, pin 2 is ground, and pin 3 is +5 V out. Note Insulate the metal heat sink tab of the regulator from traces and vias on the PCB. LM2940CT X4692 Pin1 Figure 3-3 LM2940CT +5 V Regulator Xilinx Development System...

  • Page 69: Reset Pushbutton (Sw4)

    FPGA Design Demonstration Board RESET Pushbutton (SW4) Depending on how the Reset signal routing is configured the RESET pushbutton switch can apply an active-Low Reset signal to the FPGAs and configuration PROMs. Reset is normally pulled High through a 27 kilohm resistor. SPARE Pushbutton (SW5) The SPARE pushbutton applies an active-Low signal to the XC3020A on pin 16, and to the XC4003E on pin 18.
  • Page 70 FPGA probe point header. The following table lists the FPGA pin connections. Table 3-2 Input Switch Pin Connections Switch XC3020A XC4003E SW3–1 SW3–2 SW3–3 SW3–4 SW3–5 SW3–6 SW3–7 SW3–8 Xilinx Development System...

  • Page 71: Seven-Segment Displays (U6, U7, U8)

    FPGA Design Demonstration Board Seven-Segment Displays (U6, U7, U8) Three seven-segment displays are included with the leftmost display (U6) connect to the XC3020A FPGA. The rightmost two displays (U7 and U8) connect to the XC4003E device. Each LED segment is turned on by driving the corresponding FPGA pin ‘LOW’...

  • Page 72: Led Indicators (D1-D8, D9-D16)

    XC4003E. You can turn on an LED by driving its corresponding FPGA pin Low with a logic "0." The following table shows the pin connections for the LED indicators. Table 3-4 LED Indicators for XC3020A and XC4003E XC3020A Pin XC4003E Pin 3-10 Xilinx Development System...

  • Page 73: I/O Line Connections

    FPGA Design Demonstration Board I/O Line Connections There are 16 I/O lines that connect the XC3020A and XC4003E FPGAs. These are shown in the following table. Table 3-5 I/O Line Connections for XC3020A and XC4003E Devices I/O Line XC3020A Pin XC4003E Pin Optional Crystal Oscillator (Y1) You can add a standard 4-pin crystal oscillator to the FPGA Demon-...

  • Page 74: Xc4003E Components

    There are also locations for filter capacitors. XC4003E Components This section describes the components on the FPGA Demonstration Board which are used with the XC4003E device. The following sche- matic shows this device. 3-12 Xilinx Development System...

  • Page 75: Xc4003E Fpga And Socket (U5)

    FPGA Design Demonstration Board 4.7K TRIG CLKI CLKO LD101VR RN18 RN19 PGCK1 DOUT TDI-I/O TCK-I/O INP3 TMS-I/O XC4003E 4.7K SGCK2 PGCK3 PROG DATA OPTION CCLK OE/R DONE 1765 PROG INIT RN13 RN15 100K RN12 RN14 MBR030 U1, U2 7, 8 18, 52 1, 35 6 4 2...

  • Page 76: Xc4003E Probe Points

    PROM is loaded into the XC4003E. Note MPE and SPE must not be on at the same time, one must be off when the other is on. MPE and SPE are only used in conjunction with 3-14 Xilinx Development System...

  • Page 77: M0, M1, M2-Mode Pins (Sw2-4,5,6)

    FPGA Design Demonstration Board the serial PROMs. The serial PROMs must be configured as OE/Reset to allow MPE and SPE to function properly. M0, M1, M2-Mode Pins (SW2-4,5,6) These three switches must be on to configure the XC4003E using the XChecker/Parallel Cable III.
  • Page 78 Connects to XC4003E DIN input pin 71. J2-13 PROG Provides program J2-14 Boundary scan mode pulse causing the input to the XC4003E. FPGA to configure. Connects to pin 17. Connects to XC4003E PROG input pin 55. 3-16 Xilinx Development System...

  • Page 79: Jumper J7 And Tiepoints J10 (1-3)

    FPGA Design Demonstration Board Table 3-6 XChecker/Parallel Cable III Connector J2 Name Function Name Function J2-15 INIT Goes Low if CRC J2-16 CLK1 A system clock input to error occurs during XChecker Cable to be configuration. controlled and output on Connects to CLK0.

  • Page 80: Xc3020A Components

    INP3 XTL1 XC3020A DOUT CCLK PWRDN 4.7K 100K OPTION 100K 0.1uF 0.1uF DATA CCLK DONE OE/R PROG INIT 1765 MCLK DOUT 100K VOUT 5VREG 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF X9242 Figure 3-7 XC3020A Schematic 3-18 Xilinx Development System...

  • Page 81: Xc3020A Fpga And Socket (U4)

    FPGA Design Demonstration Board XC3020A FPGA and Socket (U4) The XC3020A FPGA occupies socket U4 on the demonstration board. XC3020A Probe Points All pins of the XC3020A FPGA connect to the headers that surround the FPGA socket. These pins provide convenient points for probing signals or making wirewrap connections to other circuitry, such as the prototype area.

  • Page 82: Mpe-Multiple Program Enable (Sw1-2)

    PROMs must be configured as OE/RESET to allow MPE and SPE to function properly. M0, M1, M2-Mode Pins (SW1-4,5,6) To configure the XC3020A using the XChecker/Parallel Cable III these switches must be on. This places the FPGA in slave serial mode. 3-20 Xilinx Development System...

  • Page 83: Mclk-Master Clock (Sw1-7)

    FPGA Design Demonstration Board To configure from the onboard serial PROM, these switches must be off. This places the FPGA in master serial mode. MCLK-Master Clock (SW1-7) When this switch is on, it connects the XC4003E configuration clock (pin 73) to the configuration clock on the XC3020A (pin 60). This connection is used to configure FPGAs in a daisy chain with the XC4003E at the head.
  • Page 84 XC3020A input pin J1–9 Starts configuration J1–10 N.C. and indicates completion. Connects to XC3020A DONE/ PROGRAM pin 45. J1–11 Provides configura- J1–12 N.C. tion data during configuration. Connects to XC3020A DIN input pin 58. J1–13 N.C. J1–14 N.C. 3-22 Xilinx Development System...

  • Page 85: Serial Prom Socket (U1)

    FPGA Design Demonstration Board Table 3-7 XChecker/Parallel Cable III Connector J1 Name Function Name Function J1–15 N.C.b J1–16 CLKI System clock input to XChecker Cable to be controlled and output on CLKO. Connects to tiepoint J3–2. J1–17 Connects to jumper J1–18 CLKO System clock output...
  • Page 86 100 Hz. The following figure shows the RC Network waveforms. X4715 Figure 3-10 RC Network Waveforms The formula for calculating the RC network is as follows. T = T1 + T2 = N ((R1C5) + (R2C6)) where: 3-24 Xilinx Development System...

  • Page 87: Mode Switch Settings

    FPGA Design Demonstration Board N = approximately 0.35 for TTl threshold = approximately 0.75 for CMOS threshold when the FPGA allows each capacitor to discharge during the oppo- site timing phase. Mode Switch Settings This section describes the SW1 and SW2 switch settings for config- uring the XC3020A and XC4003E devices.
  • Page 88 XC3020A FPGA from the serial PROM. Table 3-10 Configuring the XC3020A from the Serial PROM (Single Program) Switch Name Position Switch Name Position SW1–1 SW2–1 SW1–2 SW2–2 SW1–3 SW2–3 SW1–4 SW2–4 SW1–5 SW2–5 SW1–6 SW2–6 3-26 Xilinx Development System...
  • Page 89 FPGA Design Demonstration Board Table 3-10 Configuring the XC3020A from the Serial PROM (Single Program) Switch Name Position Switch Name Position SW1–7 MCLK SW2–7 SW1–8 DOUT SW2–8 INIT X indicates don’t care The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC4003E FPGA from the serial PROM.
  • Page 90 XC3020A and XC4003E FPGAs in a daisy-chain from the XChecker/Parallel Cable III. Table 3-14 Configuring the XC3020A and XC4003E in a Daisy Chain from the XChecker/Parallel Cable III Switch Name Position Switch Name Position SW1–1 SW2–1 SW1–2 SW2–2 SW1–3 SW2–3 3-28 Xilinx Development System...
  • Page 91 FPGA Design Demonstration Board Table 3-14 Configuring the XC3020A and XC4003E in a Daisy Chain from the XChecker/Parallel Cable III Switch Name Position Switch Name Position SW1–4 SW2–4 SW1–5 SW2–5 SW1–6 SW2–6 SW1–7 MCLK SW2–7 SW1–8 DOUT SW2–8 INIT X indicates don‘t care The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A and XC4003E FPGAs in a daisy-chain from the serial PROM (single program).

  • Page 92: Demonstration Board Operation

    Power for the MultiLINX Cable” section of the “Cable Hardware” chapter. Demonstration Designs Demonstration designs are supplied with Xilinx Foundation™ and Alliance™ Series software. You can view or edit the demonstration designs. Before editing, you must compile the input files with your design implementation software.

  • Page 93: Design Downloading Checklist

    LED bar graphs of the FPGA Demonstration board. Please read the text files that accompany these designs. Design sche- matics are available by calling the Xilinx Technical Support Hotline. You can also access schematics through the Xilinx web site, located at http://www.xilinx.com. Design Downloading Checklist You must follow the recommended design flow to assure proper operation.

  • Page 94: Loading With A Configuration Prom

    If you already have a design programmed in a PROM, skip to step 5. You can also view or edit the demonstration designs supplied with the Xilinx software tools. Note Make backups before making changes to any demonstration design files.

  • Page 95: Starting Hardware Debugger

    Debugger software. For further information, consult the Hardware Debugger Guide. Open your Alliance or Foundation software. From within Xilinx Design Manager (version M1.0 or later), select Hardware Debugger from the tools menu. You can also start the Hardware Debugger from the operating system prompt by entering the following command.

  • Page 96: Tutorials

    DONE pin went High. At this point, the loaded bit file func- tions as designed. Tutorials Tutorials are available from the Xilinx Web site and on the AppLINX CD. (The Web site location is http://support.xilinx.com/support/ techsup/tutorials/index.htm). Please contact your local Sales Repre- sentative for a copy of the AppLINX CD.

  • Page 97: Cpld Design Demonstration Board

    Chapter 4 CPLD Design Demonstration Board The CPLD Design Demonstration Board (Part Number : HW-CPLD- DEMOBD) is a tool used for demonstrating the In-System Program- ming (ISP) capabilities of the XC9500 CPLD family. Using this board, you can easily program, erase, verify, and functionally test any XC9500 device.

  • Page 98: Printed Circuit Board (Pcb)

    These power supply components can be purchased from Digi-Key, as shown in the following table. Table 4-1 Digi-Key Parts List Digi-Key Part Quantity Descriptions References Number DPDT Switch, EG1909 right angle. Xilinx Development System...

  • Page 99: Demonstration Board Schematics

    CPLD Design Demonstration Board Table 4-1 Digi-Key Parts List Digi-Key Part Quantity Descriptions References Number 5V, 1A, low LM2940CT-5.0 dropout reg. 22uf, 16V, P2040 Tantalum cap. • Digi-Key Corporation is located at 701 Brooks Ave. South, Thief River Falls, MN 56701-0677, Tel: 800-344-4539, Fax: 218-681-3380, (http://www.digikey.com).
  • Page 100 32 31 30 29 25 24 22uF GTS2 0.1uF GTS1 XC9536 GCK1 GCK2 TRIG DISCH THRES .047uF CONT RESET X8087 TLC555 Figure 4-1 XC9536 Device Schematic The following figure shows the pin layout and components of the ISP Demonstration Board. Xilinx Development System...

  • Page 101: Foundation Design Tutorial

    • JCT_VHD (VHDL only) • JCT_SVHD (schematic with VHDL macro) Example I: Schematic Design Entry Example 1 shows the readme.txt file that is located in the project directories of the Jcounter tutorial designs in the Xilinx Foundation Hardware User Guide...

  • Page 102: Schematic With Vhdl Macro Design

    The counter is triggered on rising edge of the clock(CLK). The following is the sequence of states on outputs Q Q7-Q0: 00000000 00000001 00000011 00000111 00001111 00011111 00111111 01111111 11111110 11111110 11111100 11111000 11110000 11100000 11000000 10000000 00000000 (repeats) SIMULATION WAVEFORMS: Xilinx Development System...

  • Page 103: Example 2: Vhdl Design Entry

    The JEDEC programming file produced by this project can be downloaded into the CPLD Demo Board (HW-CPLD-DEMOBD). Example 2: VHDL Design Entry Example 2 shows the same design, done in VHDL while using Xilinx Foundation software. library IEEE; use IEEE.std_logic_1164.all library metamor;...
  • Page 104 Dout (7 downto 1) <= Dout (6 downto 0);--shift - Dout (7 downto 1) <= Dout (6 downto 0);--shift - Dout (0) <= not Dout (7);--Last bit inverted -- -- back into first bit end if; end process; end jcounter_arch; Xilinx Development System...
  • Page 105 Glossary Baud Rates Baud rates refer to your host system communication capabilities. Configuration Modes Configuration Modes are the modes available on the Xilinx configuration cables. They include JTAG, SelectMAP and Slave Serial. CPLD Complex Programmable Logic Device (CPLD) is an erasable programmable logic device that can be programmed with a schematic or a behavioral design.
  • Page 106 MultiLINX devices: Virtex, Spartan, XC9500, XC5200, and XC4000. MultiLINX Cable The MultiLINX cable is a device for configuring and verifying Xilinx FPGAs and CPLDs. MultiLINX Flying Wires The MultiLINX flying wires consist of four sets that are included with the MultiLINX Cable.
  • Page 107 RS-232 Port The RS-232 Port is where the MultiLINX cable connects to on the host computer. This is how the MultiLINX cable hardware communicates with the host. SelectMAP Mode SelectMAP mode is a MultiLINX configuration mode supported by the MultiLINX device, Virtex. Slave Serial Mode Slave Serial Mode is a MultiLINX configuration mode supported by the following MultiLINX devices: Virtex, Spartan,...
  • Page 108 Hardware User Guide Glossary-4 Xilinx Development System...

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