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A.2
HSDC Pro Settings for Optional ADC Device Configuration
A.2.1
Changing the Number of Serial Output Lanes (L)
The ADC device outputs data on two lanes (one lane per channel) by default, but the device may also be
configured to output on four total lanes. This option is selected using the L parameter on the JESD204B
tab in the Configuration GUI. In this case, 'LM97937EVM_421' must be selected as the device in HSDC
Pro.
A.2.2
Changing the Number of Frames per Multi-Frame (K)
Changing the number of frames per multi-frame output by the JESD204 transmitter (ADC device) is
configured using the K parameter on the JESD204B tab in the Configuration GUI. This parameter must be
matched by the receiving device, but configuration of the K parameter of the receiver is not supported at
this time.
A.3
Exercising the SYSREF Input of the ADC
The SYSREF input is used to align the phase of the internal local multi-frame clock (LMFC) of the ADC,
according to the JESD204B interface specification, but it is not required to establish a link and evaluate
the analog performance of the ADC with this EVM. Upon power-up, the ADC assumes a default alignment
for its LMFC and proceeds to synchronize with the receiving device without requiring a SYSREF input
event.
A SYSREF signal may be applied to the ADC via the SYSREF SMA connector on the EVM to validate the
response of the ADC to a SYSREF event. The SYSREF signal path is AC coupled; therefore only periodic
signals with frequencies > 5 MHz are supported.
TI does not recommend use of the SYSREF SMA input of the EVM to ensure deterministic latency across
the serial link, due to difficulties of controlling timing requirements. The on-board LMK04828 may be used
in an optional configuration to clock both the ADC and receiving device to achieve deterministic latency.
A.4
Customizing the EVM for Optional Clocking Support
By default, the LMK04828 is configured as a clock distributer and divider and only provides clock signals
to the receiving FPGA device. The EVM is configured to require an ADC device clock from an external
signal generator source through the CLK SMA connector. These default configurations are intentional as
they allow the most flexibility for ADC sampling rates and they allow the highest ADC performance
possible.
The LMK04828 may be reconfigured to exercise more features, but this EVM is not intended to be a full
evaluation platform for the LMK04828. A full evaluation platform can be found on the LMK04828
page.
A.4.1
LMK04828 Configuration Options
Configuring the LMK04828 is possible in a couple different ways. TI recommends to use the 'Configuration
3' button on the LMK tab of the Configuration GUI. By pressing this button, a text file containing register
values is accessed and the contents are written to the device registers. The text file is stored in the
Configuration GUI installation directory in the '\Configuration Files' folder and is called
'LMK04828_config3.cfg'. The register values in this file may be edited manually. The LMK04828
sheet
and the CodeLoader 4 software may aid the design and editing process.
A second method for configuring the LMK04828 is to populate the programming header 'LMKSPI' with
associated passive components to enable communication over the header and disable access of the SPI
bus via the USB-to-SPI FTDI chip by placing a jumper on the JP2 header. Once the EVM is reconfigured
to support this option, the CodeLoader 4 software and associated programming cable may be used to
directly configure the LMK04828. Refer to the LMK04828 evaluation platform for proper configuration of
the LMKSPI header.
SLAU542 – December 2013
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HSDC Pro Settings for Optional ADC Device Configuration
Copyright © 2013, Texas Instruments Incorporated
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