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3.2
Peripherals
The 5509 supports the following peripherals:
•
A Configurable Parallel External Interface supporting either:
−
16-bit external memory interface (EMIF) for asynchronous memory and/or SDRAM
−
16-bit enhanced host-port interface (HPI)
•
A six-channel direct memory access (DMA) controller
•
A programmable digital phase-locked loop (DPLL) clock generator
•
Two 20-bit timers
•
Watchdog Timer
•
Three serial ports supporting a combination of:
−
up to three multichannel buffered serial ports (McBSPs)
−
up to two MultiMedia/Secure Digital Card Interfaces
•
Seven (LQFP) or Eight (BGA) configurable general-purpose I/O pins
•
USB full-speed slave interface supporting:
−
Bulk
−
Interrupt
−
Isochronous
•
2
I
C multi-master and slave interface (I
•
Real-time clock with crystal input, separate clock domain and supply pins
•
4-channel (BGA) or 2-channel (LQFP)10-bit Successive Approximation A/D
For detailed information on the C55x DSP peripherals, see the following documents:
•
TMS320C55x DSP Functional Overview (literature number SPRU312)
•
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
3.3
Direct Memory Access (DMA) Controller
The 5509 DMA provides the following features:
•
Four standard ports, one for each of the following data resources: DARAM, SARAM, Peripherals and
External Memory
•
Six channels, which allow the DMA controller to track the context of six independent DMA channels
•
Programmable low/high priority for each DMA channel
•
One interrupt for each DMA channel
•
Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected
events.
•
Programmable address modification for source and destination addresses
•
Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software
control.
•
Dedicated DMA channel used by the HPI to access internal memory (DARAM)
The 5509 DMA controller allows transfers to be synchronized to selected events. The 5509 supports
19 separate sync events and each channel can be tied to separate sync events independent of the other
channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel
Control Register (DMA_CCR).
April 2001 − Revised January 2008
2
C compatible except, no fail-safe I/O buffers)
Functional Overview
SPRS163H
37
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