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Chapter 4: Connecting the Emulator to a Target System
Plugging The Emulator Into A Target System
A double bus fault occurs when the processor encounters an exception that
prevents processing of a previous exception. An example of a double bus fault is
shown above. This original exception occurred because the target system tried to
execute an illegal instruction. During processing of the illegal instruction
exception, the processor encountered another exception.
This exception was an address error caused because the vector supplied for the
illegal instruction handler was odd. The double bus fault occurred when the vector
supplied for the address error handler was also odd. Other things that can cause a
double bus fault are bus errors that occur during exception stacking or vector fetch.
Keep in mind that bus errors can happen because the target system asserts BERR.
Once you have found the cause of the double bus fault, you need to determine the
root cause of the problem. In some cases, the exception is a normal part of
execution, but the subsequent faults indicate a problem. In some cases, the first
fault indicates a problem directly, such as when the program has already
malfunctioned, and the fault is caused by an unintentional access.
At this point, the problem is to find the faulty bus cycle that eventually caused a
recognizable problem. The same situation exists if the processor stops execution at
an address that should not have been executed, or if a program is simply running
code incorrectly.
There are really only two ways to go about determining what is wrong. - One is to
try to trace back the terminal error condition to a faulty bus cycle. - The other is to
start at the beginning of the trace, or at some other known point, and work forward,
comparing the trace to the execution that was expected while looking for the point
where execution first becomes unexpected. A listing of the program or a tracelist
captured by a preprocessor could be used for this comparison.
When you find a suspected bus cycle, set up a trigger on it so that you can make a
timing measurement on the cycle. When looking for clues or shortcuts to the
problem, keep in mind that a system is usually made up of many different types of
memory devices: ROM, EEPROM, SRAM, DRAM, and peripheral ports. Each of
these devices may have different timing characteristics. Also, keep in mind that
unique characteristics of a bus cycle, such as size and number of wait states, may
result in unique timing requirements.
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