HP 64782 Series Manual page 151

Num Characteristic
31 DSACK[1:0] Asserted to Data In Valid
33 Clock Low to BG Asserted/Negated
35 BR Asserted to BG Asserted (RMC Not
Asserted)
37 BGACK Asserted to BG Negated
39 BG Width Negated
39A BG Width Asserted
46 R/W Width Asserted (Write or Read)
46A R/W Width Asserted (Fast Write or
Read Cycle)
47A Asynchronous Input Setup Time BR,
BGACK, DSACK[1:0], BERR, AVEC,
HALT
47B Asynchronous Input Hold Time
48 DSACK[1:0] Asserted to BERR,
HALT Asserted
53 Data Out Hold from Clock High
54 Clock High to Data Out High
Impedance
55 R/W Asserted to Data Bus Impedance
Change
HP 64782 — AC TIMING SPECIFICATIONS
= 5.0 Vdc ±10%, V
( and V
V DD
DDSYN
Chapter 9: Specifications and Characteristics
HP 64782 AC Timing Specifications
= 0 Vdc)
SS
16.78 MHz 20.97 MHz
Min Max Min
— 50 —
— 27 —
1 — 1
1 2 1
2 — 2
1 — 1
150 — 115
90 — 70
10 — 10
13 — 10
— 30 —
-5 — -5
— 26 —
40 — 32
Unit
Max
46 ns
21 ns
— t
cyc
2 t
cyc
— t
cyc
— t
cyc
— ns
— ns
— ns
— ns
30 ns
— ns
21 ns
— ns
139