Status Register (Sr); Sr Bits - Texas Instruments MSP430x5 series User Manual

CPU Registers

6.3.3 Status Register (SR)

The 16-bit Status Register (SR, also called R2), used as a source or destination register, can only be used
in register mode addressed with word instructions. The remaining combinations of addressing modes are
used to support the constant generator.
SR. Unpredictable operation can result.
15
Table 6-1 describes the SR bits.
Bit Description
Reserved Reserved
V Overflow. This bit is set when the result of an arithmetic operation overflows the signed-variable range.
ADD(.B), ADDX(.B,.A),
ADDC(.B), ADDCX(.B.A),
ADDA
SUB(.B), SUBX(.B,.A),
SUBC(.B),SUBCX(.B,.A),
SUBA, CMP(.B),
CMPX(.B,.A), CMPA
SCG1 System clock generator 1. This bit may be used to enable or disable functions in the clock system depending on the
device family; for example, DCO bias enable or disable.
SCG0 System clock generator 0. This bit may be used to enable or disable functions in the clock system depending on the
device family; for example, FLL enable or disable.
OSCOFF Oscillator off. When this bit is set, it turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or
SMCLK.
CPUOFF CPU off. When this bit is set, it turns off the CPU.
GIE General interrupt enable. When this bit is set, it enables maskable interrupts. When it is reset, all maskable interrupts
are disabled.
N Negative. This bit is set when the result of an operation is negative and cleared when the result is positive.
Z Zero. This bit is set when the result of an operation is 0 and cleared when the result is not 0.
C Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred.
NOTE: Bit manipulations of the SR should be done by the following instructions: MOV, BIS, and
BIC.
192
CPUX
Figure 6-9
9 8
Reserved V
rw-0
Figure 6-9. SR Bits
Table 6-1. SR Bit Description
Copyright © 2008–2018, Texas Instruments Incorporated
shows the SR bits. Do not write 20-bit values to the
7
OSC CPU
SCG1 SCG0 GIE
OFF OFF
Set when:
positive + positive = negative
negative + negative = positive
otherwise reset
Set when:
positive – negative = negative
negative – positive = positive
otherwise reset
SLAU208Q – June 2008 – Revised March 2018
www.ti.com
0
N Z C
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