Priority Queue Status Register (Pqsr) - Texas Instruments TMS320C6000 DSP Reference Manual

EDMA Control Registers
2.6.2

Priority Queue Status Register (PQSR)

Figure 2−5. Priority Queue Status Register (PQSR)
31
Legend: R = Read only; -n = value after reset
Table 2−11. Priority Queue Status Register (PQSR) Field Descriptions
Bit Field
symval
31−3 Reserved −
2−0 PQ OF(value)
†
For CSL implementation, use the notation EDMA_PQSR_PQ_symval.
2-14 TMS320C621x/C671x EDMA
The priority queue status register (PQSR) indicates whether the transfer
request queue is empty on the priority level queues. The PQSR is shown in
Figure 2−5 and described in Table 2−11. The priority queue status (PQ) bit
provides the status of the queues. When the PQ bits are set to 111b, there are
no requests pending in the respective priority level queues. For example, if
bit 0 (PQ0) is set to 1, all L2 requests for data movement have been completed
and there are no requests pending in the priority level 0 queue.
The PQ bits are mainly used for emulation, context switching for multitasking
applications, and submitting requests with a higher priority (when possible).
In the emulation case, bit 0 ensures that all cache requests using L2 are
completed before updating any memory windows for the emulation halt. The
PQ bits also determine the right time to do a task switch. For example, it allo-
cates L2 SRAM to a new task, after ensuring that there are no EDMA transfer
requests in progress that might write to L2 SRAM. Lastly, the PQ bits allocate
or submit requests judiciously on the lower priority levels (by the EDMA or HPI)
depending on which priority queue is empty. Therefore, it can upgrade a low-
priority request to a high priority if required. This helps prevent all requests from
being queued under the same priority level, which could lead to EDMA stalls.
Perform writes to PQSR only when the corresponding queues are empty of all
outstanding transfer requests, through event disabling and checking the PQ bits.
Reserved
R-0
† Value Description
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
0−7h Priority queue status bits. A 1 in the PQ bit indicates that there are
no requests pending in the respective priority level queue.
3 2 1 0
PQ2 PQ1 PQ0
R-1 R-1 R-1
SPRU234