Table of Contents
Advertisement
3 SPECIFICATIONS
3.3 I/O Signals for the PLC CPU
3.3.1 I/O signal list
QJ71DN91
Input number
Signal name
X00
Watchdog Timer Error
X01
I/O Communicating
Message Communication
X02
Completion
X03
Master Function For Error Set Signal
X04
Slave Down Signal
Message Communication Error
X05
Signal
Saving Parameter To The Flash
X06
ROM
Save Parameter To Flash ROM
X07
Completion
X08
Slave Function For Error Set Signal
X09
Use prohibited
X0A
H/W Testing
X0B
H/W Test Completion
X0C
H/W Test Error Detection
X0D
Use prohibited
X0E
X0F
Module Ready
X10
X11
Use prohibited
X12
X13
X14
Auto Configuration Executing
X15
Auto Configuration Completion
X16
X17
X18
X19
Use prohibited
X1A
X1B
X1C
X1D
X1E
X1F
3 - 13
This section explains the input/output signals for the PLC CPU of the QJ71DN91.
The I/O signal list for the QJ71DN91 is shown in Table 3.2.
The I/O numbers (X/Y) and I/O addresses described from this chapter are applicable
when the QJ71DN91 is installed in slot 0 of the basic base module.
Table 3.2 I/O signal list
PLC CPU
Usability
Master
function
—
—
At the time of the
hardware test
At the time of the
hardware test
At the time of the
hardware test
—
—
—
IMPORTANT
The use-prohibited output signals shown in Table 3.2 are accessed by the system
and cannot be accessed by the user. In the event these signals are used (turned
ON/OFF) by the user, normal operations cannot be guaranteed.
Output number
Slave
function
Y00
Y01
—
Y02
—
Y03
—
Y04
—
Y05
Y06
Y07
Use prohibited
Y08
—
Y09
Y0A
Y0B
Y0C
Y0D
—
Y0E
Y0F
Y10
Y11
I/O Communication Request
—
Y12
Message Communication Request
Master Function For Error Reset
Y13
Request
—
Y14
Use prohibited
—
Y15
Auto Configuration Request
Y16
Use prohibited
Save Parameter To Flash ROM
Y17
Request
Slave Function For Error Reset
Y18
Request
Y19
—
Y1A
Y1B
Y1C
Use prohibited
Y1D
Y1E
Y1F
MELSEC-Q
PLC CPU
QJ71DN91
Signal name
Usability
Master
Slave
function
function
—
—
—
—
—
—
—
—
—
—
—
—
3 - 13
Advertisement
Table of Contents
