Mitsubishi QJ71DN91 User Manual page 111

7 PROGRAMMING WHEN EXECUTING THE MASTER FUNCTION
PLC CPU
X100 to X107
X110 to X14F
X160 to X16F
Y100 to Y107
Y110 to Y14F
7 - 3
The following shows the relationships among the PLC CPU, master node buffer
memory and each slave node.
QJ71DN91 master node
Reception data
FROM
Node No. 1 reception
700
H
701
H
Node No. 4
FROM 702
H
703
H
704
H
Node No. 3 status
705
H
FROM
Node No. 3 reception
706
H
Transmission data
TO
Node No. 2
transmission
900
H
901
H
902
H
TO
Node No. 4
903 transmission
H
904
H
Node No. 3
905 transmission
H
reception
MELSEC-Q
Remote I/O (Node No. 1)
8-point input
I00 to I07
Input 00 to input 07
QJ71DN91 slave node (node No. 4)
8-byte transmission/reception
C00
H
C01
H
Transmission data
C02
H
C03
H
B00
H
B01
H Reception data
B02
H
B03
H
Remote I/O (node No. 3)
16-point input
Status
I00 to I15
Input 00 to input 15
Dummy output
Remote I/O (node No. 2)
8-point input
O00 to O07
Output 00 to output 07
7 - 3