Mitsubishi QJ71LP21 Reference Manual page 317

8 TROUBLESHOOTING
Error
Code Error Contents and Cause
*1
(SD0)
The parameter setting is illegal.
• Though Block 0 was set to
3200 "Automatic start" in the SFC setting
of the PLC parameter dialog box,
Block 0 does not exist.
3201 The block parameter setting is illegal.
The number of step relays specified in
the device setting of the PLC
3202
parameter dialog box is less than that
used in the program.
The execution type of the SFC
program specified in the program
3203
setting of the PLC parameter dialog
box is other than scan execution.
The start I/O number in the intelligent
function module parameter set on
3300
GX Configurator differs from the actual
I/O number.
The refresh setting of the intelligent
function module exceeded the file
register capacity.
3301
The intelligent function module's
refresh parameter setting is outside
the available range.
The intelligent function module's
3302
refresh parameter are abnormal.
In a multiple CPU system, the
automatic refresh setting or other
3303 parameter setting was made to the
intelligent function module under
control of another station.
*1 : Characters in parentheses ( ) indicate the special register numbers where individual information is being
stored.
*12 : This applies to the CPU module of function version B or later.
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Corrective Action
Read the common information of the
error using the peripheral device,
check error step corresponding to its
numerical value (program error
location), and correct the problem.
Check the parameter setting.
Change the file register file for the one
which allows refresh in the whole
range.
Check the parameter setting.
Check the parameter setting.
• Delete the automatic refresh setting
or other parameter setting of the
intelligent function module under
control of another CPU.
• Change the setting to the automatic
refresh setting or other parameter
setting of the intelligent function
module under control of the host
CPU.
MELSEC-Q
Corresponding
CPU
QnA
Q00J/Q00/
*12
Q01
QnPH
QnPRH
QnA
Qn(H)
QnPH
QnPRH
QCPU
Rem
Q00J/Q00/Q01
*12
Qn(H)
QnPH
QnPRH
QCPU
Rem
QCPU
*12
Q00/Q01
*12
Qn(H)
QnPH
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