Rx Equalizer - Xilinx 7 Series User Manual

RX Equalizer

Functional Description
The GTP transceiver receiver has a power-efficient adaptive continuous time linear equalizer
(CTLE) to compensate for signal distortion due to high-frequency attenuation in the physical
channel. To maintain parity with the 7 series FPGAs GTX and GTH transceivers, the CTLE is
referred to as the low-power mode (LPM).
The LPM mode (see
with line rates up to 6.6 Gb/s for short reach applications, with channel losses of 12 dB or less at the
Nyquist frequency.
X-Ref Target - Figure 4-15
Ports and Attributes
Table 4-9
Table 4-9: RX Equalizer Ports
RXLPMRESET
RXLPMHFHOLD
RXLPMHFOVRDEN
RXLPMLFHOLD
RXLPMLFOVRDEN
Table 4-10
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 4-15) has adaptive low and high frequency boosts. It is for applications
P
Termination
N
Figure 4-15: RX Equalization Block Diagram
defines the RX equalizer ports.
Port Dir
In
In
In
In
In
defines the RX equalizer attributes.
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CTLE
Clock Domain
Async Resets the LPM circuitry.
Async When set to 1'b1, the current value of the
high-frequency boost is held.
When set to 1'b0, the high-frequency boost is
adapted.
Async When set to 1'b1, the high-frequency boost is
controlled by the RXLPM_HF_CFG attribute.
When set to 1'b0, the high-frequency boost is
controlled by the RXLPMHFHOLD signal.
Async When set to 1'b1, the current value of the
low-frequency boost is held.
When set to 1'b0, the low-frequency boost is
adapted.
Async When set to 1'b1, the low-frequency boost is
controlled by the RXLPM_LF_CFG attribute.
When set to 1'b0, the low-frequency boost is
controlled by the RXLPMLFHOLD signal.
RX Equalizer
CDR
UG482_c4_05_110911
Description
139
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