Enabling Comma Alignment; Configuring Comma Patterns - Xilinx 7 Series User Manual

Figure 4-26
after comma alignment on the right side.
X-Ref Target - Figure 4-26

Enabling Comma Alignment

To enable the comma alignment block, the RXCOMMADETEN port is driven High.
RXCOMMADETEN is driven Low to bypass the block completely for minimum latency.

Configuring Comma Patterns

To set the comma pattern that the block searches for in the incoming data stream, the
ALIGN_MCOMMA_VALUE, ALIGN_PCOMMA_VALUE, and ALIGN_COMMA_ENABLE
attributes are used. The comma lengths depend on RX_DATA_WIDTH (see
Figure 4-27
partial pattern matching.
X-Ref Target - Figure 4-27
Figure 4-28
X-Ref Target - Figure 4-28
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows TX parallel data on the left side, and RX receiving recognizable parallel data
TX Parallel Data
Data0
Comma
Data1
Data2
Figure 4-26: Parallel Data View of Comma Alignment
shows how the ALIGN_COMMA_ENABLE masks each of the comma values to allow
ALIGN_MCOMMA_VALUE
or
ALIGN_PCOMMA_VALUE
0 1 0 1 1 1 1 1 0 0
0 0 0 1 1 1 1 1 1 1
ALIGN_COMMA_ENABLE
Figure 4-27: Comma Pattern Masking
shows how the commas are combined when ALIGN_COMMA_DOUBLE is TRUE.
ALIGN_MCOMMA_VALUE
Figure 4-28: Extended Comma Pattern Definition
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RX Byte and Word Alignment
RX Parallel Data
Non-aligned
Data
Comma
Time
Data1
Data2
UG482_c4_15_110911
Pattern Required for
Comma Detection
ALIGN_PCOMMA_VALUE
UG482_c4_17_111011
Send Feedback
Table 4-47, page 216).
(x = Don't Care)
x x x 11 1 11 0 0
UG482_c4_16_111011
161