Overview And Features - Xilinx 7 Series User Manual

Transceiver and Tool Overview

Overview and Features

The 7 series FPGAs GTP transceiver is a power-efficient transceiver, supporting line rates between
500 Mb/s and 6.6 Gb/s. The GTP transceiver is highly configurable and tightly integrated with the
programmable logic resources of the FPGA.
that support a wide variety of applications.
Table 1-1: 7 Series FPGAs Transceiver Features
Group
PCS 2-byte internal datapath
4-byte internal datapath
8B/10B encoding and decoding
64B/66B and 64B/67B support
Comma detection and byte and word alignment
PRBS generator and checker
FIFO for clock correction and channel bonding
Programmable FPGA logic interface
PMA One shared LC tank PLL per Quad
One ring oscillator PLL per channel
Two shared ring oscillator PLLs per Quad
Flexible reference clocking options
Decision feedback equalization (DFE)
Power-efficient adaptive linear equalizer mode called the low-power mode (LPM)
TX Pre-emphasis
Beacon signaling for PCI Express® designs
Out-of-band (OOB) signaling including COM signal support for Serial ATA (SATA)
designs
RX Margin Analysis
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Table 1-1 summarizes the features by functional group
Feature
www.xilinx.com
Chapter 1
GTP GTX GTH
x x x
x x
x x x
x x x
x x x
x x x
x x x
x x x
x x
x x
x
x x x
x x
x x x
x x x
x x x
x x x
x x x
11
Send Feedback