Revision History - Xilinx 7 Series User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
01/03/2012 1.0
02/21/2012 1.1
01/01/2012 1.1.1
09/06/2012 1.2
7 Series FPGAs GTP Transceivers User Guide
Initial Xilinx release.
Changed "N" factor to "N1" and "N2"factors in
Revised Figure A-4, Figure A-6,
Made typographical edits.
Updated the second, third, and fourth paragraphs under
Updated description of PLL0_FBDIV/PLL1_FBDIV and added PLL0_FBDIV_45/
PLL0_FBDIV_45 attributes to
Chapter 2. Updated Note 1 relevant to
TXSTARTSEQ and GEARBOX_MODE attributes in
domains and descriptions in
TXPI_GREY_SEL attribute descriptions in
under TX Gearbox Operating Modes in Chapter
Mode section in Chapter 3, Transmitter. Added USE_PCS_CLK_PHASE_SEL and
ES_CLK_PHASE_SE attributes to
Alignment Status Signals in Chapter
RXBYTEISALIGNED port in
Table 4-26. Updated description of GEARBOX_MODE attribute in
Chapter 5, Board Design Guidelines. Updated all package drawings in
Information by Package. Updated
www.xilinx.com
Revision
Figure 2-10, Equation 2-1, and
Table B-1, Table D-1, and
Overview and Features in Chapter
Table 2-9. Added Reset and Initialization
Figure 3-2 through
Table
Table 3-26. Updated TXPI_SYNFREQ_PPM[2:0] and
Table 3-27. Updated first introductory paragraph
3. Deleted Internal Sequence Counter Operating
Table 4-20. Added second and third paragraphs under
4. Added last sentence to description of
Table 4-25. Added COMMA_ALIGN_LATENCY attribute to
Table B-1.
Table 2-7.
Table D-2.
and Power Down in
Figure 3-5. Updated descriptions of
3-9. Updated controller port clock
Table 4-42. Added
Appendix A, Placement
UG482 (v1.9) December 19, 2016
1.