Rx Channel Bonding - Xilinx 7 Series User Manual

Fpgas gtp transceivers
Hide thumbs Also See for 7 Series:
Table of Contents

Advertisement

X-Ref Target - Figure 4-46
To preserve comma alignment through the elastic buffer, CLK_COR_SEQ_LEN and
ALIGN_COMMA_WORD must be selected such that they comply with
Table 4-38: Valid ALIGN_COMMA_WORD/CLK_COR_SEQ_LEN Combinations
Clock Correction Options
CLK_COR_REPEAT_WAIT is used to control the clock correction frequency. This value is set to
the minimum number of RXUSRCLK cycles required between clock correction events. This
attribute is set to 0 to allow clock correction to at occur any time. Some protocols allow clock
correction to occur at any time, but require that if the clock correction circuit removes sequences, at
least one sequence stays in the stream. For protocols with this requirement,
CLK_COR_KEEP_IDLE is set to TRUE.
Monitoring Clock Correction
The clock correction circuit can be monitored using the RXCLKCORCNT and RXBUFSTATUS
ports. The RXCLKCORCNT entry in
RXCLKCORCNT to determine the status of the clock correction circuit. The RXBUFSTATUS
entry in
RX elastic buffer is.

RX Channel Bonding

Functional Description
Protocols such as XAUI and PCI Express combine multiple serial transceiver connections to create
a single higher throughput channel. Each serial transceiver connection is called one lane. Unless
each of the serial connections is exactly the same length, skew between the lanes can cause data to
be transmitted at the same time but arrive at different times. Channel bonding cancels out the skew
between GTP transceiver lanes by using the RX elastic buffer as a variable latency block. Channel
bonding is also called channel deskew or lane-to-lane deskew. GTP transceiver transmitters used for
a bonded channel all transmit a channel bonding character (or a sequence of characters)
simultaneously. When the sequence is received, the GTP transceiver receiver can determine the
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
CLK_COR_SEQ_x_4
CLK_COR_SEQ_x_3
Figure 4-46: Clock Correction Sequence Mapping
ALIGN_COMMA_WORD
1
2
Table 4-36
shows how to decode the values of RXBUFSTATUS to determine how full the
www.xilinx.com
CLK_COR_SEQ_x_2
4
3
2
1
CLK_COR_SEQ_x_ENABLE
CLK_COR_SEQ_LEN
Table 4-36
shows how to decode the values of
RX Channel Bonding
CLK_COR_SEQ_x_1
UG482_c4_28_111011
Table
4-38.
1, 2, 4
2, 4
Send Feedback
197

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents