Interrupt Inputs (Counter Mode) - Omron CJ1M-CPU21 Operation Manual

Built-in Inputs
Restrictions on Interrupt
Inputs (Direct Mode)
Specifications

Interrupt Inputs (Counter Mode)

Overview
Bit Allocations
• Interrupt inputs 0 to 3 cannot be used when built-in inputs IN0 to IN3 are
being used as general-purpose inputs or quick-response inputs.
• Interrupt input 3 cannot be used when high-speed counter input 0 is being
used and the high-speed counter 0 reset method is set to Phase-Z signal
+ Software reset.
Interrupt input 2 cannot be used when high-speed counter input 1 is being
used and the high-speed counter 1 reset method is set to Phase-Z signal
+ Software reset.
• Interrupt inputs 0 and 1 cannot be used when the origin search function is
enabled for pulse output 0 (enabled in the PLC Setup).
Interrupt inputs 2 and 3 cannot be used when the origin search function is
enabled for pulse output 1 (enabled in the PLC Setup).
Item
Number of inputs
Allocated data area
Interrupt detection
Interrupt Task Numbers
Input bit
CIO 2960 bit 00
CIO 2960 bit 01
CIO 2960 bit 02
CIO 2960 bit 03
This function counts input signals (up or down differentiated) and starts an
interrupt task when the counter PV reaches the SV (or 0 when decrementing.)
The four interrupt inputs control interrupt tasks 140 to 143. The interrupt task
numbers cannot be changed.
Code Word address
IN0 CIO 2960
IN1
IN2
IN3
Specifications
4 inputs (The 4 input terminals are shared with the
quick-response inputs, high-speed counter (Phase-Z
signal), and general-purpose inputs.)
CIO 2960 bits 00 to 03
Up differentiation or down differentiation
Interrupt task number
140
141
142
143
Bit
00
01
02
03
Section 6-1
Function
Interrupt input 0
Interrupt input 1
Interrupt input 2
Interrupt input 3
127