Omron CJ1M-CPU21 Operation Manual page 100

Auxiliary Area Data Allocation
Name Address
High-speed Counter A27509
1
Overflow/Underflow
Flag
High-speed Counter A27510
1
Count Direction
High-speed Counter A53100
0 Reset Bit
High-speed Counter A53101
1 Reset Bit
High-speed Counter A53108
0 Gate Bit
High-speed Counter A53109
1 Gate Bit
Description
This flag indicates when an overflow or under-
flow has occurred in the high-speed counter 1
PV. (Used only when the counting mode is set to
Linear Mode.)
0: Normal
1: Overflow or underflow
This flag indicates whether the high-speed
counter is currently being incremented or decre-
mented. The counter PV for the current cycle is
compared with the PC in last cycle to determine
the direction.
0: Decrementing
1: Incrementing
When the reset method is set to Phase-Z signal
+ Software reset, the corresponding high-speed
counter's PV will be reset if the phase-Z signal is
received while this bit is ON.
When the reset method is set to Software reset,
the corresponding high-speed counter's PV will
be reset in the cycle when this bit goes from
OFF to ON.
When a counter's Gate Bit is ON, the counter's
PV will not be changed even if pulse inputs are
received for the counter.
When the bit is turned OFF again, counting will
restart and the high-speed counter's PV will be
refreshed.
When the reset method is set to Phase-Z signal
+ Software reset, the Gate Bit is disabled while
the corresponding Reset Bit (A53100 or
A53101) is ON.
Section 4-3
Read/Write Times when data is
accessed
Read only • Cleared when
power is turned
ON.
• Cleared when
operation starts.
• Cleared when the
PV is changed.
• Refreshed when
an overflow or
underflow occurs.
Read only • Setting used for
high-speed
counter, valid dur-
ing counter opera-
tion.
Read/write • Cleared when
power is turned
ON.
Read/write
Read/write • Cleared when
power is turned
ON.
Read/write
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