Panasonic UF-5500 Service Manual page 194

UF-5500 / 4500
Pin No Signal Name
30 LED0 / NWAYEN
31 LED1 / SPEED
32 RST#
PAD- GND
DLE
NOTE:
• P = Power supply.
Gnd = Ground.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
• MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC
through the MII. RXD[3..0] is invalid when RXDV is de-asserted.
• RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits
of recovered data are sent from the PHY.
• MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the
Input/Output(*)
Ipu/O LED Output: Programmable LED0 Output /
Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12)
during power-up / reset. See "Strapping Options" section for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is
defined as follows.
LED mode = [00]
Link/Activity
No Link
Link
Activity
LED mode = [01]
Link
No Link
Link
LED mode = [10]
Reserved
LED mode = [11]
Reserved
Ipu/O LED Output: Programmable LED1 Output /
Config Mode: Latched as SPEED (register 0h, bit 13) during power-up /
reset. See "Strapping Options" section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is
defined as follows.
LED mode = [00]
Speed
10BT
100BT
LED mode = [01]
Activity
No Activity
Activity
LED mode = [10]
Reserved
LED mode = [11]
Reserved
I Chip Reset (active low)
Gnd Ground
194
Description
Pin State LED Definition
H OFF
ON
L
Toggle Blinking
Pin State LED Definition
H OFF
L ON
Pin State LED Definition
H OFF
L ON
Pin State LED Definition
H OFF
Toggle Blinking