Panasonic UF-5500 Service Manual page 193

IC750 (C1CB00002566 : 3.3V Single Power Supply) Pin Description
Pin No Signal Name
1 GND
2 VDDPLL_1.8
3 VDDA_3.3
4 RX-
5 RX+
6 TX-
7 TX+
8 XO
9 XI / REFCLK
10 REXT
11 MDIO
12 MDC
13 RXD3 / PHYAD0
14 RXD2 / PHYAD1
15 RXD1 /
RXD[1] /
PHYAD2
16 RXD0 /
RXD[0] /
DUPLEX
17 VDDIO_3.3
18 RXDV /
CRSDV /
CONFIG2
19 RXC
20 RXER /
RX_ER /
ISO
21 INTRP
22 TXC
23 TXEN / TX_EN
24 TXD0 / TXD[0]
25 TXD1 / TXD[1]
26 TXD2
27 TXD3
28 COL / CONFIG0
29 CRS / CONFIG1
Input/Output(*)
Gnd Ground
P 1.8V analog VDD
P 3.3V analog VDD
I/O Physical receive or transmit signal (- differential)
I/O Physical receive or transmit signal (+ differential)
I/O Physical transmit or receive signal (- differential)
I/O Physical transmit or receive signal (+ differential)
O Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or
if RMII mode is selected.
I Crystal / Oscillator / External Clock Input
MII Mode: 25MHz +/-50ppm (crystal, oscillator, or external clock) RMII
Mode: 50MHz +/-50ppm (oscillator, or external clock only)
I/O Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground
on this pin. See KSZ8041NL reference schematics.
I/O Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
I Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
Ipu/O MII Mode: Receive Data Output[3](2) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0]
during power-up / reset. See "Strapping Options" section for details.
Ipd/O MII Mode: Receive Data Output[2](2) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1]
during power-up / reset. See "Strapping Options" section for details.
Ipd/O MII Mode: Receive Data Output[1](2) /
RMII Mode: Receive Data Output[1](3) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2]
during power-up / reset. See "Strapping Options" section for details.
Ipu/O MII Mode: Receive Data Output[0](2) /
RMII Mode: Receive Data Output[0](3) /
Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See "Strapping Options" section for details.
P 3.3V digital VDD
Ipd/O MII Mode: Receive Data Valid Output /
RMII Mode: Carrier Sense/Receive Data Valid Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG2 dur-
ing power-up / reset. See "Strapping Options" section for details.
O MII Mode: Receive Clock Output
Ipd/O MII Mode: Receive Error Output /
RMII Mode: Receive Error Output /
Config Mode: The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See "Strapping Options" section for details.
Opu Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming
the interrupt conditions and reading the interrupt status. Register 1Fh bit
9 sets the interrupt output to active low (default) or active high.
O MII Mode: Transmit Clock Output
I MII Mode: Transmit Enable Input /
RMII Mode: Transmit Enable Input
I MII Mode: Transmit Data Input[0](4) /
RMII Mode: Transmit Data Input[0](5)
I MII Mode: Transmit Data Input[1](4) /
RMII Mode: Transmit Data Input[1](5)
I MII Mode: Transmit Data Input[2](4) /
I MII Mode: Transmit Data Input[3](4) /
Ipd/O MII Mode: Collision Detect Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG0 dur-
ing power-up / reset. See "Strapping Options" section for details.
Ipd/O MII Mode: Carrier Sense Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG1 dur-
ing power-up / reset. See "Strapping Options" section for details.
193
Description
UF-5500 / 4500