Status Register; Status-Register Bit Definition - IBM AT 5170 Technical Reference

=-i . - - -
RAM on the system board
N .--- Manufacturing mode
p .---
Display type
U
T .--- Keyboard Inhibited
Input
Buffer
~ ~
==
~~~~e~2~eset
. 1 - - - -
U - IRQ I
T - Keyboard Clock---,-+
System
Data Output
+----1 ' - . . . .
= ======
-
Keyboa r d D a t a --+---.-+
Bus Buffer
TPu
,--2_K_Rg_~_8----,~
------iill]
+-_ _ _ _ _ _---'
Keyboard Controller Interface Block Diagram
Status Register
The status register is an 8-bit read-only register at I/O address
hex 64.
It
has information about the state of the keyboard
controller (8042) and interface. It may be read at any time.
Status-Register Bit Definition
Bit 7 Parity Error-A 0 indicates the last byte of data received
from the keyboard had odd parity. A 1 indicates the last
byte had even parity. The keyboard should send data
with odd parity.
Bit 6 Receive Time-Out-A 1 indicates that a transmission was
started by the keyboard but did not finish within the
programmed receive time-out delay.
~
Bit 5 Transmit Time-Out-A 1 indicates that a transmission
started by the keyboard controller was not properly
completed. If the transmit byte was not clocked out
within the specified time limit, this will be the only error.
System
Board 1-49