IBM AT 5170 Technical Reference page 26

DMA controller 2 contains channels 4 through 7. Channel 4 is
used to cascade channels 0 through 3 to the microprocessor.
Channels 5, 6, and 7 support 16-bit data transfers between 16-bit
I/O adapters and 16-bit system memory. These DMA channels
can transfer data throughout the 16M system-address space in
128K blocks. Channels 5, 6, and 7 cannot transfer data on
odd-byte boundaries.
Source
DMA Page Registers
Controller
Address A23<---------->A17 A16<---------->Al
Address Generation for DMA Channels 5 through 7
Note: The addressing signals, BHE and AO, are forced to a
10gicalO.
The following figure shows the addresses for the page register.
Page Register
liD
Hex Address
DMA Channel 0
0087
DMA Channel 1 0083
DMA Channel 2 0081
DMA Channel 3 0082
DMA Channel 5 008B
DMA Channel 6 0089
DMA Channel 7
008A
Refresh 008F
Page Register Addresses
Addresses for all DMA channels do not increase or decrease
through page boundaries (64K for channels 0 through 3, and
128K for channels 5 through 7).
DMA channels 5 through 7 perform 16-bit data transfers. Access
can be gained only to 16-bit devices (I/O or memory) during the
DMA cycles of channels 5 through 7. Access to the DMA
controller, which controls these channels, is through I/O
addresses hex
oeo
through ODF.
1-10
System Board