System Clock; Rom Subsystem - IBM AT 5170 Technical Reference

+5 Vdc
-Refresh Refresh Request
D Q
Clock
L -
Clear
Bus _ _
System
Gate 0
-
Clock In 0
+5 Vdc Gate I
~
Clock In
1
I/O Add
ress
Hex 006 I -
-
Gate 2
Port Bi t 0
~
Clock In 2
IRQ 0
Clock Out 0
Clock Out I
-
I
Driver
I
Clock Out 2
Low
f---+
To Speaker
I/O Add
ress
Pass
I
AND
I
Hex 006 I
F
i Iter
Port Bi t I
PC LK
Divide
I
(2
.38MHz)
by 2
System-Timer Block Diagram
System Clock
The 82284 System Clock Generator is driven by a 12-MHz
crystal. Its output
I
clock
I
signal (CLK) is the input to the system
microprocessor, the coprocessor, and I/O channel.
ROM Subsystem
The system board's ROM subsystem consists of two 32K by 8-bit
~
ROM/EPROM modules in a 32K-by-16-bit arrangement. The
code for odd and even addresses resides in separate modules.
ROM is assigned at the top of the first and last 1M address space
(OFOOOO and FFOOOO). ROM is not parity-checked. Its access
time is 150 nanoseconds and its cycle time is 230 nanoseconds.
System Board 1-23