IBM AT 5170 Technical Reference page 50

-SMEMR (0) -MEMR (I/O)
These signals instruct the memory devices to drive data onto the
data bus. -SMEMR is active only when the memory decode is
within the low 1M of memory space. -MEMR is active on all
memory read cycles. -MEMR may be driven by any
microprocessor or DMA controller in the system. -SMEMR is
derived from -MEMR and the decode of the low 1M of memory.
When a microprocessor on the
I/O
channel wishes to drive
-MEMR, it must have the address lines valid on the bus for one
clock cycle before driving -MEMR active. Both signals are active
low.
-SMEMW (0) -MEMW (I/O)
These signals instruct the memory devices to store the data
present on the data bus. -SMEMW is active only when the
memory decode is within the low 1M of the memory space.
-MEMW is active on all memory write cycles. -MEMW may be
driven by any microprocessor or DMA controller in the system.
-SMEMW is derived from -MEMW and the decode of the low
1M of memory. When a microprocessor on the
I/O
channel
~
wishes to drive -MEMW, it must have the address lines valid on
the bus for one clock cycle before driving -MEMW active. Both
signals are active low.
DRQO-DRQ3 and DRQ5-DRQ7
(I)
The
I
DMA request
I
signals 0 through 3 and 5 through 7 are
asynchronous channel requests used by peripheral devices and a
microprocessor to gain DMA service (or control of the system).
They are prioritized, with DRQO having the highest priority and
DRQ7 the lowest. A request is generated by bringing a DRQ line
to an active (high) level. A DRQ line is held high until the
corresponding
I
DMA acknowledge
I
(DACK) line goes active.
DRQO through DRQ3 perform 8-bit DMA transfers; DRQ5
through DRQ7 perform 16-bit transfers. DRQ4 is used on the
system board and is not available on the 110 channel.
1-34 System Board