IBM AT 5170 Technical Reference page 51

-DACKO
to
-DACK3 and -DACK5
to
-DACK7 (0)
-DMA acknowledge 0 through 3 and 5 through 7 are used to
acknowledge DMA requests. These signals are active low.
AEN (0)
The
I
address enable
I
signal is used to degate the microprocessor
and other devices from the I/O channel to allow DMA transfers
to take place. When this line is active, the DMA controller has
control of the address bus, the data-bus Read command lines
(memory and I/O), and the Write command lines (memory and
I/O). This signal is active high.
-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by
a microprocessor on the I/O channel. This signal is active low.
T/C (0)
The
I
terminal count
I
signal provides a high pulse when the
terminal count for any DMA channel is reached.
SBHE (I/O)
The
I
system bus high enable
I
signal indicates a transfer of data
on the upper byte of the data bus, SD8 through SD15.
Sixteen-bit devices use SBHE to condition data bus buffers tied to
SD8 through SD15. This signal is active high.
-MASTER (I)
r'""\
This signal is used with a DRQ line to gain control of the system.
A processor or DMA controller on the I/O channel may issue a
DRQ to a DMA channel in cascade mode and receive a -DACK.
Upon receiving the -DACK, a microprocessor may pull
System Board 1-35