IBM AT 5170 Technical Reference page 52

-MASTER active (low), which will allow it to control the system
address, data, and control lines (a condition known as tri-state).
After -MASTER is low, the microprocessor must wait one clock
cycle before driving the address and data lines, and two clock
cycles before issuing a Read or Write command. If this signal is
held low for more than 15 microseconds, the system memory may
be lost because of a lack of refresh.
-MEM CS16
(I)
The '-memory 16-bit chip select' signal indicates to the system
that the present data transfer is a 1 wait-state, 16-bit, memory
cycle.
It
must be derived from the decode of LA17 through
LA23. -MEM CS16 is active low and should be driven with an
open collector or tri-state driver capable of sinking 20 mA.
-I/O CS16
(I)
The '-I/O 16-bit chip select' signal indicates to the system that
the present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is
derived from an address decode. -I/O CS16 is active low and
r--...
should be driven with an open collector or tri-state driver capable
of sinking 20 mA.
OSC (0)
The 'oscillator' signal is a high-speed clock with a
70-nanosecond period (14.31818 MHz). This signal is not
synchronous with the system clock. It has a 50% duty cycle.
OWS (I)
The 'zero wait state' signal tells the microprocessor that it can
complete the present bus cycle without inserting any additional
wait cycles. In order to nm a memory cycle to a 16-bit device ~
without wait cycles, OWS is derived from an address decode gated
with a Read or Write command. In order to run a memory cycle
to an 8-bit device with a minimum of two wait states, OWS should
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System
Board