IBM AT 5170 Technical Reference page 66

If the transmit byte was clocked out but a response was
not received within the programmed time limit, the
transmit time-out and receive time-out error bits are set
to 1. If the transmit byte was clocked out but the
response was received with a parity error, the transmit
time-out and parity error bits are set to 1.
Bit 4
Inhibit Switch-This bit is updated whenever data is
placed in the keyboard controller's output buffer. It
reflects the state of the keyboard-inhibit switch. A 0
indicates the keyboard is inhibited.
Bit 3
Command/Data-The keyboard controller's input buffer
may be addressed as either I/O address hex 60 or 64.
Address hex 60 is defined as the data port, and address
hex 64 is defined as the command port. Writing to
address hex 64 sets this bit to 1; writing to address hex 60
sets this bit to O. The controller uses this bit to determine
if the byte in its input buffer should be interpreted as a
command byte or a data byte.
Bit 2
System Flag-This bit is monitored by the system during
the reset routine. If it is a 0, the reset was caused by a
~
power on. The controller sets this bit to 0 at power on
and it is set to
1
after a successful self test. This bit can
be changed by writing to the system flag bit in the
command byte (hex 64).
Bit 1
Input Buffer Full-A 0 indicates that the keyboard
controller's input buffer (I/O address hex 60 or 64) is
empty. A 1 indicates that data has been written into the
buffer but the controller has not read the data. When the
controller reads the input buffer, this bit
will
return to O.
Bit 0
Output Buffer Full-A 0 indicates that the keyboard
controller's output buffer has no data. A 1 indicates that
the controller has placed data into its output buffer but
the system has not yet read the data. When the system
reads the output buffer (I/O address hex 60), this bit will
return to a O.
~
1-50
System
Board