IBM AT 5170 Technical Reference page 211

Table of Contents

Advertisement

IBM Personal Computer MACRO
TESTI
----
06/10/85
POWER ON
1085
1086
1087
1088
1089
1090
1091 019F
1092 a 19F 80 03
1093 alAI
E6
80
1094
1095 01A3 89 0009
1096 01A6 84 01
1097 01A8
1098 01A8 80 8F
1099 01AA E6 70
1100 01AC 8A C4
1101
01AE E6 71
1I0201BOB08F
1103 01B2 90
1104 0lB3 E6 70
1105 0lB5 90
11060186 E4 71
1107 0lB8 3A C4
11080lBA7592
1109 018C DO 04
1110 018E E2 E8
11I1
112
"'
II.
II.
II.
117
118
119
120 OICO B8 ---- R
121 0le3 8E 08
122 0lC5 BO 04
123 alC7 E6 80
1124
1125
1126
1127 alC9 E6 08
1128 OICB E6 DO
,129
1130
1131
1132 OICD 88
16 0072
R
1133 0101
BO 54
1134 0103 E6 43
1135 0105 E8 00
1136 0107 8A Cl
1137 0109 E6 41
1138 OIDB 87 05
1139 0100
1140 0100 BO 40
1141 OIOF E8 00
11420lEIE643
'143 01E3 80 FB FF
1144 0lE6
74
OB
1145 0lE8 E4 41
1146 OlEA OA 08
1147 alEC E2 EF
1148 alEE FE CF
1149 OtFO 75 E8
1150 0 I F2 F4
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162 0lF3 BO 05
1163 0lF5 E6 80
1164
1165 01F7 8A C3
1166 0lF9 2B C9
1167 alFS
E6
41
11680lFDB705
1169 OIFF
1170 OIFF 80 40
I I 71 0201 E6 43
1172 0203 E8 00
1173 0205 EB 00
11740207 E4 41
1175 0209 22 08
1176 020B 74 07
1 177 0200 E2 Fa
1178 020F FE CF
1179 021175 EC
1180 0213 F4
'81
182
'8'
18'
18'
18.
187
188
189
190
191
192
19'
19.
195 0214
196 0214 B8 ---- R
197 0217 8E 08
1980219 BO 06
Ass.mbLer
lIerSion 2.00
1-12
SELF TEST {POSTI
06-10-85
; DESCRIPTION
1
ROLLI NG BIT WR I TTEN AND
;
IIER I FlED AT SHUTDOWN ADDRESS.
;
- -
---
-
---
-- - - -
---- -
-
-
- - - -- - ---
-- ---
- -
-
- ­
IIER I FY AND CLEAR SHUTOOWN FLAG
"OV
AL,03H
OUT
MFG_PORT, AL
"OV
CX,09H
"OV
AH,I
CIIBI
"OV
AL, CMOS SHUT OOWN+NM I
OUT
CMOS_PORT .AL­
"OV
AL.AH
OUT
CMOS_OATA,AL
"OV
AL. CMOS_SHUT _DOWN+NM I
NOP
OUT
CMOS _PORT. AL
NOP
IN
AL,CMOS_DATA
C"P
AL,AH
JNZ
ERRO I
RCL
LOOP
AH,'
CIIB
;
-
- -
-----------------------------
- -
-----­
I TEST.04
I
;
8254 CHECK TIMER I ALL BITS ON
:
; DESCRIPTION
,
,
SET T I MER COUNT
I
I
CHECK THAT TIMER
1 ALL 81TS ON
:
1---------- --- ------------ - - ------------­
ASSUME
DS:DATA
MOil
AX,DATA
MOil
DS.AX
MOil
AL,04H
OUT
MFG_PORT .AL
o
I SABLE DMA CONTROLLER
OUT
DMA08,AL
OUT
DMAI8.AL
;----- IIERIFY THAT TIMER! FUNCTIONS OK
MOil
ox.
GIIRESET FLAG
MOV
AL.54H­
OUT
T [MER+3. AL
.JMP
1+2
MOil
AL.CL
OUT
T[MER+[ .AL
MOil
BH,05H
C12;
MOV
AL,40H
JMP
1+2
OUT
TlMER+3,AL
CMP
BL.OFFH
JE
CI3
IN
AL,TIMER+[
OR
8L.AL
LOOP
Cl2
DEC
BH
JNZ
CI2
HLT
;
-- -
--
- --- - - - -
----- - --
- -
---
- - -- -- - - --
---­
I
TEST.05
:
I
8254 CHECK TIMER 1 ALL BIT OFF
1
I DESCRIPTION
I
SET T
I
MER COUNT
:
I
CHECK THAT TIMER
1 ALL BITS OFF:
:
-
-
- -
------- - - -
--- --- ---- --- - -----
-
--
- -
- ­
;-----
CHECK PO I NT 05
C13;
MDV
AL,05H
DUT
MFG_PORT ,AL
MDV
AL,BL
SUB
cX,ex
OUT
TIMER+I.AL
MOV
BH,05H
C14:
"OV
AL,40H
OUT
TlMER+3.AL
J""
'.2
J"P
1·2
IN
AL,TIMER+t
AND
BL,AL
JZ
CI'
LOOP
CI'
OEC
BH
JNZ
CI'
HLT
;
--------------------------------- ------­
; TE5T.06
8237 DMA
0
INITIALIZATION
CHANNEL REG
I
STER TEST
DESCRIPTION
I
DISABLE THE 8237 OMA CONTROLLER.:
WRITE/READ THE CURRENT ADDRESS
:
AND WORO COUNT REG I STERS FOR
ALL CHANNELS.
;
---------------
- -
----------------------­
;-----
CHECKPOINT 06
CIS:
MOil
AX,DATA
MOil
DS,AX
MOV
AL,06H
-<>-<>-<> -<> -<><><> -<>-<> -<><>-<>
0<>
CHECKPOINT
03
<><>
LOOP COUNT
START WITH BIT 0
OUTPUT ROLL
I
NG B [T
READ CMOS
110 DELAY
110 DELAY
MUST BE THE SAME
ERROR IF NOT
ROLL A BIT THROUGH SHUTDOWN BYTE
LOOP TILL DONE
SET DATA SEGMENT
<> <><><><><><><><> <><> <>
<><>
CHECKPOINT
04
<><>
{ALI
ALREADY
=
04H
o
I SABLE OMA CONTROLLER
I
o
I SABLE DMA CONTROLLER 2
SAllE RESET FLAG WHI LE REFRESH I S OFF
SELECT T I MER I, LSB, MODE 2
I/O DELAY
SET INITIAL TIMER COUNT TO 0
LOOP COUNT
TIMER 1 81TS ON
LATCH TIMER-l COUNT
110 DELAY
YES -
SEE IF ALL 81TS GO OFF
TIMERI BITS OFF
READ TTMER
T
COUNT
ALL BITS ON
IN TIMER
TlMERI_8ITS_ON
TRY AGAIN
TIMER
I
FAILURE, HALT SYSTEM
TIMERI_BITS_OFF
<><><> <><> <> <><><><><><>
<><>
CHECKPO I NT
05
<><>
SET TIMER I COUNT
SET TRY AGA I N COll\lT
TIMER LOOP
LATCH-T I MER
I COUNT
DELAY FOR TIMER
ADDED DELAY FOR T I MER
READ TIMER I COUNT
GO TO WRAP DMA REG I STER TESTS
TIMER_LOOP
HALT SYSTEM
SET DATA SEGMENT
TESTl
5-39

Advertisement

Table of Contents
loading

Table of Contents