IBM AT 5170 Technical Reference page 53

be driven active one clock cycle after the Read or Write command
is active, and gated with the address decode for the device.
Memory Read and Write commands to an 8-bit device are active
on the falling edge of eLK. OWS is active low and should be
driven with an open collector or tri-state driver capable of sinking
20 rnA.
The following figure is an
I/O
address map.
Hex Range Device
000-01F DMA controller I, 8237A-5
020-03F Interrupt controller I, 8259A, Master
040-05F Timer 8254-2
060-06F 8042 lKeyboard)
070-07F
Real-time clock, NMI (non-maskable interrupt) mask
080-09F DMA page register, 74LS612
DAO-OBF
Interrupt Controller 2, 8259A
OCO-ODF
DMA controller 2, 8237A-5
OFO Clear Math Coprocessor Busy
OFI Reset Math Coprocessor
DF8-0FF
Math Coprocessor
Note: I/O Addresses, hex 000 to OFF, are reserved for the
system board I/O. Hex 100 to 3FF are available on the I/O
channe I.
/~
I/O Address Map (Part 1 of 2)
System Board 1-37