IBM AT 5170 Technical Reference page 49

I/O eH RDY (I)
The 'I/O channel ready' signal is pulled low (not ready) by a
memory or I/O device to lengthen I/O or memory cycles. Any
slow device using this line should drive it low immediately upon
detecting its valid address and a Read or Write command.
Machine cycles are extended by an integral number of clock
cycles (167 nanoseconds). This signal should be held low for no
more than 2.5 microseconds.
IRQ3-IRQ7, IRQ9-IRQ12, IRQ14, and IRQ15 (I)
Interrupt requests 3 through 7,9 through 12,14, and 15 are used
to signal the microprocessor that an I/O device needs attention.
The interrupt requests are prioritized, with IRQ9 through IRQ 12,
IRQI4, and IRQ15 having the highest priority (IRQ9 is the
highest), and IRQ3 through IRQ7 having the lowest priority
(IRQ7 is the lowest). An interrupt request is generated when an
IRQ line is raised from low to high. The line is high until the
microprocessor acknowledges the interrupt request (Interrupt
Service routine).
Note: Interrupt 13 is used on the system board and is not
available on the I/O channel. IRQ 8 is used for the real-time
clock.
-lOR (I/O)
The '-I/O read' signal instructs an I/O device to drive its data
onto the data bus. This signal may be driven by the system
microprocessor or DMA controller, or by a microprocessor or
DMA controller resident on the I/O channel. This signal is active
low.
-lOW (I/O)
The '-I/O write' signal instructs an I/O device to read the data
off the data bus. It may be driven by any microprocessor or
DMA controller in the system. This signal is active low.
System Board
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