IBM AT 5170 Technical Reference page 74

Bit 3-Bit 0 Rate Selection Bits (RS3 through RSO)-These
bits allow the selection of a divider output
frequency. The system initializes the rate
selection bits to 0110, which selects a 1.024-kHz
square wave output frequency and a
976.562-microsecond periodic interrupt rate. ".-.....
Status Register B
Bit 7 Set-A 0 updates the cycle normally by
advancing the counts at one-per-second. A 1
aborts any update cycle in progress and the
program can initialize the 14 time-bytes without
any further updates occurring until a 0 is written
to this bit.
Bit 6 Periodic Interrupt Enable (PIE)-This bit is a
read/write bit that allows an interrupt to occur at
a rate specified by the rate and divider bits in
register A. A 1 enables an interrupt, and a 0
disables it. The system initializes this bit to O.
Bit 5
Alarm Interrupt Enable (AIE)-A 1 enables the
alarm interrupt, and a 0 disables it. The system
initializes this bit to O.
Bit 4
Update-Ended Interrupt Enabled (UIE)-A 1
enables the update-ended interrupt, and a 0
disables it. The system initializes this bit to O.
Bit 3 Square Wave Enabled (SQWE)-A 1 enables the
the square-wave frequency as set by the rate
selection bits in register A, and a 0 disables the
square wave. The system initializes this bit to O.
Bit 2 Date Mode (DM)-This bit indicates whether
the time and date calendar updates are to use
binary or binary coded decimal (BCD) formats.
A 1 indicates binary, and a 0 indicates BCD. The
system initializes this bit to
o.
1-58 System Board