Pioneer PRV-LX10 Service Manual page 172

1
XC2S50-5PQ208C (AVIB ASSY : IC5004)
• LTC Switch FPGA
A
Pin Function
No. Pin Name I/O
−
1 GNDDI GND
−
2 TMS TEST Pin
3 27MWMK O 27MHz clock for WMIC
4 LTC IN I Time code input
Component level switch
5 B/XS O
"L"=BETA, "H"=SMPTE
−
6 RESERVE Resereved
AV through output switch
7 THSW O
B
"L"=Non, "H"=THROU
8 SCL O For I2C communication (not used)
9 SDA. O For I2C communication (not used)
Input video switching signal "L"=CVBS, "H"=S
10 VSEL1 O
−
11 GNDDI GND
−
12 V+3_3I +3.3V
−
13 V+2_5I +2.5V
14 VSEL2 O
Input video switching signal "L"=CV/S, "H"=TCbCr
15 G_ADD7 I George656 video data
16 G_ADD6 I George656 video data
C
17 G_ADD5 I George656 video data
18 G_ADD4 I George656 video data
−
19 GNDDI GND
20 G_ADD3 I George656 video data
21 G_ADD2 I George656 video data
22 G_ADD1 I George656 video data
23 G_ADD0 I George656 video data
24 G_NONSI I Nonstandard 656 flag
−
25 GNDDI GND
−
26 V+3_3I +3.3V
D
Audio input switching signal "L"=RCA, "H"=XLR
27 XSELXLR O
−
28 V+2_5I +2.5V
29 ADATI I ADC data
30 BCKI I ADC block clock
31 LRCKI I ADC LR clock
−
32 GNDDI GND
33 FDATI O Multiplex audio data
34 FBCKI O Multiplex audio clock
35 FLRCKI O Multiplex audio LR clock
E
−
36 RESERVE Reserved
37 MCIF_ACKZ I DV acknowledge signal
−
38 V+2_5I +2.5V
−
39 V+3_3I +3.3V
−
40 GNDDI GND
41 MCIF_STRBZ
O DV strobe signal
42 GPIO3_WM0
I DV control signal
43 HSDIA_AV I DV control signal
44 HSDIA_EN O DV control signal
F
45 HSDIA_CLK O Clock for DV (LINK) IC
172
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2
Pin Function No. Pin Name I/O
PRV-LX10
2
3
46 DVREQ I DV control signal
47 DVACK O DV control signal
48 DVFRM I DV control signal
49 WAITDVX I DVXcel wait signal
50 M1 I Mode setting (pull-up)
−
51 GNDDI GND
52 M0 I Mode setting (ground)
−
53 V+3_3I +3.3V
54 M2 I Mode setting (pull-up)
−
55 N.C.
Not used
−
56 N.C. Not used
57 TBCLK O Clock for DVXceL
Clock selection at SDI input at SDI select: H
58 SDICKSEL O
PLL gain switch of DV input at DV input: L
59 DVCSEL I
60 DVOEN I DV control signal
61 XWAITV O DV control signal
62 WAITDVSH O DV control signal
63 LXRD I Host bus read signal
−
64 GNDDI GND
−
65 V+3_3I +3.3V
−
66 V+2_5I 2.5V
67 SEL27M O Not used
68 AV1_LRCK I Decoder audio LR clock
69 AV1_BCK I Decoder audio clock
70 AV1_DAI I Decoder audio data
SDI audio switch
71 SDI_CHSEL O
"L"=Ch3/4, "H"=Ch1/2
−
72 GNDDI GND
Error signal of AES/EBU signal
73 AES_ERROR I
"L"= Error exists, "H"= no error
74 SDI_RST I System reset signal to DINB
Lock ok signal to SDI audio
75 SDI_LOCK I
"L"= Unlock, "H"= Lock
−
76 V+2_5I +2.5V
77 36MFPGA I 36.864MHz clock for audio
−
78 V+3_3I +3.3V
−
79 GNDDI GND
80 40MPLD I 40MHz clock for configuration
81 AV1_D7 I Decoder 656 video data
82 AV1_D6 I Decoder 656 video data
83 AV1_D5 I Decoder 656 video data
−
84 AV1_D4 Decoder 656 video data
−
85 GNDDI GND
86 AV1_D3 I Decoder 656 video data
−
87 AV1_D2 Decoder 656 video data
88 AV1_D1 I Decoder 656 video data
−
89 AV1_D0 Decoder 656 video data
Copy protection existence flag
90 PCC1 I
"H" = Copy protection exists
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4
Pin Function
4