Table Of Contents - Texas Instruments TMS320C6457 User Manual

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Preface
1 Introduction to the HPI
1.1 Summary of the HPI Registers
1.2 Summary of the HPI Signals
2 Using the Address Registers
2.1 Single-HPIA Mode
2.2 Dual-HPIA Mode
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3 HPI Operation
3.1 Host-HPI Signal Connections
3.2 HPI Configuration and Data Flow
3.3 HDS2, HDS1, and HCS: Data Strobing and Chip Selection
3.4 HCNTL[1:0] and HR/W: Indicating the Cycle Type
3.5 HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode
3.6 HAS: Forcing the HPI to Latch Control Information Early
3.7 Performing a Multiplexed Access Without HAS
3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode
3.9 Hardware Handshaking Using the HPI-Ready (HRDY) Signal
4 Software Handshaking Using the HPI Ready (HRDY) Bit
4.1 Polling the HRDY Bit
5 Interrupts Between the Host and the CPU
5.1 DSPINT Bit: Host-to-CPU Interrupts
5.2 HINT Bit: CPU-to-Host Interrupts
6 FIFOs and Bursting
6.1 Read Bursting
6.2 Write Bursting
6.3 FIFO Flush Conditions
6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs
7 Emulation and Reset Considerations
7.1 Emulation Modes
7.2 Software Reset Considerations
7.3 Hardware Reset Considerations
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8 HPI Registers
8.1 Introduction
8.2 Power and Emulation Management Register (PWREMU_MGMT)
8.3 Host Port Interface Control Register (HPIC)
8.4 Host Port Interface Address Registers (HPIAW and HPIAR)
8.5 Data Register (HPID)
Appendix A Revision History
SPRUGK7A - March 2009 - Revised July 2010
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Copyright © 2009-2010, Texas Instruments Incorporated
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Table of Contents