Hrdy Behavior During An Hpic Or Hpia Read Cycle In The 16-Bit Multiplexed Mode; Hrdy Behavior During A Data Read Operation In The 16-Bit Multiplexed Mode (Case 1: Hpia Write Cycle Followed By Nonautoincrement Hpid Read Cycle); Hrdy Behavior During A Data Read Operation In The 16-Bit Multiplexed Mode; Hrdy Behavior During A Data Read Operation In The 16-Bit Multiplexed Mode (Case 2: Hpia Write Cycle Followed By Autoincrement Hpid Read Cycles) - Texas Instruments TMS320C6457 User Manual

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The following sections describe the behavior of HRDY during HPI register accesses. In all cases, the chip
select signal, HCS, must be asserted for HRDY to go high.
3.9.1 HRDY Behavior During 16-Bit Multiplexed Read Operations
Figure 12 shows an HPIC (HCNTL[1:0] = 00b) or HPIA (HCNTL[1:0] = 10b) read cycle during 16-bit
multiplexed HPI operation. Neither an HPIC read cycle nor an HPIA read cycle causes HRDY to go high.
Figure 12. HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode
HCS
HCNTL[1:0]
HR/W
HHWIL
Internal
HSTRB
HD[15:0]
HRDY
Figure 13 includes an HPID read cycle without autoincrementing in the 16-bit multiplexed mode. The host
writes the memory address during the HPIA (HCNTL[1:0] = 10b) write cycle, and the host reads the data
during the HPID (HCNTL[1:0] = 11b) read cycle. HRDY goes high for each HPIA halfword access, but
HRDY goes high for only the first halfword access in each HPID read cycle.
Figure 13. HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode
(Case 1: HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle)
HCS
HCNTL[1:0]
10
HR/W
HHWIL
Internal
HSTRB
HD[15:0]
HRDY
Figure 14 includes an autoincrement HPID read cycle in the 16-bit multiplexed mode. The host writes the
memory address while asserting HCNTL[1:0] = 10b and reads the data while asserting HCNTL[1:0] = 01b.
During the first HPID read cycle, HRDY goes high for only the first halfword access, and subsequent HPID
read cycles do not cause HRDY to go high.
Figure 14. HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode
(Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)
HCS
HCNTL[1:0]
10
HR/W
HHWIL
Internal
HSTRB
1st halfword
HD[15:0]
HRDY
SPRUGK7A – March 2009 – Revised July 2010
00 or 10
1st halfword
HPIA write
10
1st halfword 2nd halfword
HPIA write
10
2nd halfword
Copyright © 2009–2010, Texas Instruments Incorporated
00 or 10
HPID read
11
1st halfword
HPID+ reads
01 01
1st halfword 2nd halfword
HPI Operation
2nd halfword
11
2nd halfword
01
1st halfword
Host Port Interface (HPI)
23