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T r i g g e r S o u r c e
Figure 5.12: I/O trigger source
detailed timing diagram for the external trigger mode.
t
d - i s o - i n p u t
t
j i t t e r
Figure 5.13: Trigger timing diagram
The rising edge of the trigger signal is detected in the camera control electronic which is
implemented in an FPGA. Before the trigger signal reaches the FPGA it is isolated from the
camera environment to allow robust integration of the camera into the vision system. In the
signal isolator the trigger signal is delayed by time t
FPGA which leads to a jitter of t
can be configured by a user defined value via camera software. The trigger offset delay
t
results then from the synchronous design of the FPGA state machines and from to
trigger offset
requirement to start an exposure at a fixed point from the start of the read out of a row. The
exposure time t
exposure
5.2 Trigger and Strobe
F l a s h
T T L
C a m e r a 1
P o w e r
D a t a C a m e r a L i n k
T T L
t
t r i g g e r - d e l a y
t
t r i g g e r - o f f s e t
t
e x p o s u r e
t
s t r o b e - d e l a y
t
s t r o b e - o f f s e t
t
s t r o b e - d u r a t i o n
t
d - i s o - o u t p u t
. The pulse can be delayed by the time t
jitter
is controlled with an internal exposure time controller.
M a c h i n e V i s i o n
S y s t e m
C a m e r a L i n k
F r a m e G r a b b e r
T M
e x t e r n a l t r i g g e r p u l s e i n p u t
t r i g g e r a f t e r i s o l a t o r
t r i g g e r p u l s e i n t e r n a l c a m e r a c o n t r o l
d e l a y e d t r i g g e r f o r s h u t t e r c o n t r o l
i n t e r n a l s h u t t e r c o n t r o l
d e l a y e d t r i g g e r f o r s t r o b e c o n t r o l
i n t e r n a l s t r o b e c o n t r o l
e x t e r n a l s t r o b e p u l s e o u t p u t
. This signal is clocked into the
d iso input
P C
which
trigger delay
31
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