Gateway ALR 9250R User Manual page 53

support the cache on two SEC cartridges. Therefore each processor requires
1.5 VRMs. See the table Processors and Associated VRMs below for the
allowed processor and VRM configurations.
Processors and Associated VRMs
Processor VRM
Installed Installed
Processor 1 VRM 1
VRM 2
Processor 2 VRM 3
Processor 3 VRM 4
VRM 5
Processor 4 VRM 6
Processor slots
®
Each Pentium II Xeon
an SEC cartridge. The cartridge includes the processor core with an
integrated 16 KB primary (L1) cache; the secondary (L2) cache; a thermal
plate; and a back cover. The processor implements MMX
maintains full backward compatibility with the 8086, 80286, Intel386
™
Intel486 , Pentium, Pentium Pro, and Pentium II processors.
Each SEC cartridge connects to the system board through a Slot 2 edge
connector. The cartridge is secured by a retention bracket attached to the
system board. Depending on configuration, the server has one to four
processors.
The processor external interface is multiprocessor (MP)-ready and operates
at 100 MHz. The processor contains a local advanced programmable
interrupt controller (APIC) for interrupt handling in MP and uniprocessor
(UP) environments. The system SMP design supports up to four processors
and is Intel MP Specification v1.1 and 1.4 compliant.
The second-level cache is located inside the SEC cartridge. The cache
includes burst pipelined synchronous static RAM (BSRAM) and is offered
in 512 KB, 1 MB, and 2 MB configurations, with ECC that operates at the
full core clock rate.
VRM Function
Powers the processor core for processor 1
Powers the second-level cache for processors 1 and 2
Powers the processor core for processor 2
Powers the processor core for processor 3
Powers the second-level cache for processors 3 and 4
Powers the processor core for processor 4
™ ®
or Pentium III Xeon
™
processor is packaged in
™
technology and
™
,
Chapter 2: System Features 39