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Register Description (for direct hardware control)
Address
Mode
Base+0
RD/WR
Base+1
RD/WR
Base+2
RD/WR
Base+3
RD/WR
Base+4
RD/WR
Base+5
RD/WR
Base+6
RD Only
Base+7
RD Only
Note: All ports are set to input after reset or power up.
Interrupt source is Base+0 bit D0. When selecting the Interrupt Mode, always
disable interrupts prior to changing or setting states. This will help prevent
inadvertent or un-expected interrupts from occurring. When using the high and
low level interrupts, a change in state of the input must occur before the
interrupt can be cleared. The device providing the input to Base +0, bit D0 must
do this.
PAD0-7
= Port A (Base+0)
PBD0-7
= Port B (Base+1)
PCD0-7
= Port C (Base+2)
PDD0-7
= Port D (Base+3)
DIRA-D
= Port A-D direction control (Base+4)
IRC0-1= Interrupt Mode select (Base+5)
IRC1 IRC0
0
0
1
1
1
rising edge
IRQEN = enable interrupts (Base+5)
0 = disabled
1 = enabled (disabled after reset or power up).
IRQST = interrupt status (Base+5)
1 = interrupt pending (reading the bit clears interrupt).
Sealevel Systems PIO-32.PCI
D7
D6
D5
PAD7
PAD6
PAD5
PBD7
PBD6
PBD5
PCD7
PCD6
PCD5
PDD7
PDD6
PDD
5
{0}
{0}
{0}
IRQEN
IRQST
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Figure 5-Register Description
0 = input
1 = output
0
Low level
1
high level
0
falling edge
Technical Description
D4
D3
D2
PAD4 PAD3
PAD2
PBD4
PBD3
PBD2
PCD4
PCD3
PCD2
PDD
PDD
PDD
4
3
2
{0}
DIRD
DIRC
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Page 13
D1
D0
PAD1
PAD0
PBD1
PBD0
PCD1
PCD0
PDD
PDD
1
0
DIRB
DIRA
IRC1
IRC0
{0}
{0}
{0}
{0}
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