Silicon Graphics Zx10 User Manual page 73

007-4330-002
Table 5-1 (continued)
Code Beeps POST Routine Description
2Ah Clear 512 KB base RAM
2Ch 1- 3- 4- 1 or RAM failure on address line xxxx *
1- 1- 1- 1
2Eh 1- 3- 4- 3 RAM failure on data bits xxxx * of low byte of memory bus
2Fh Enable cache before system BIOS shadow
30h 1- 4- 1- 1 RAM failure on data bits xxxx * of high byte of memory bus
32h Test CPU bus clock frequency
33h Initialize Phoenix Dispatch Manager
36h Warm start shut down
38h Shadow system BIOS ROM
3Ah 1- 4- 3- 3 Autosize cache
3Ch Advanced configuration of chipset registers
3Dh Load alternate registers with CMOS values
42h Initialize interrupt vectors
45h POST device initialization
46h 2- 1- 2- 3 Check ROM copyright notice
48h Check video configuration against CMOS
49h Initialize PCI bus and devices
4Ah Initialize all video adapters in system
4Bh QuietBoot start (optional)
4Ch Shadow video BIOS ROM
4Eh Display BIOS copyright notice
50h Display CPU type and speed
51h Initialize EISA board
Test Point Codes
POST Tasks and Beep Codes
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