The Ibm Power7+ Processor - IBM Power 750 Technical Overview And Introduction

2.1 The IBM POWER7+ processor

The IBM POWER7+ processor represents a leap forward in technology achievement and
associated computing capability. The multi-core architecture of the POWER7+ processor has
been matched with innovation across a wide range of related technologies to deliver leading
throughput, efficiency, scalability, and reliability, availability, and serviceability (RAS).
Note: This section provides a general description of the POWER7+ processor chip that
applies to Power Systems servers in general. The Power 750 and Power 760 servers use
two 4- or 6-core chips packaged in a DCM.
Although the processor is an important component in delivering outstanding servers, many
elements and facilities must be balanced on a server to deliver maximum throughput. As with
previous generations of systems based on IBM POWER® processors, the design philosophy
for POWER7+ processor-based systems is one of system-wide balance in which the
POWER7+ processor plays an important role.
IBM uses innovative technologies to achieve required levels of throughput and bandwidth.
Areas of innovation for the POWER7+ processor and POWER7+ processor-based systems
include (but are not limited to) the following items:
On-chip L3 cache implemented in embedded dynamic random access memory (eDRAM)
Cache hierarchy and component innovation
Advances in memory subsystem
Advances in off-chip signaling
Advances in I/O card throughput and latency
Advances in RAS features such as power-on reset and L3 cache dynamic column repair
The superscalar POWER7+ processor design also provides a variety of other capabilities:
Binary compatibility with the prior generation of POWER processors
Support for PowerVM virtualization capabilities, including PowerVM Live Partition Mobility
to and from POWER6, POWER6+, and POWER7 processor-based systems
Figure 2-2 on page 46 shows the POWER7+ processor die layout, with the major areas
identified:
Processor cores
L2 cache
L3 cache and chip interconnection
Simultaneous multiprocessing links
Memory controllers.
I/O links
Chapter 2. Architecture and technical overview
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