IBM Power 750 Technical Overview And Introduction page 64

Figure 2-5 shows the FLR-L3 cache regions for each of the cores on the POWER7+
processor die.
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Figure 2-5 Fast local regions of L3 cache on the POWER7+ processor
The innovation of using eDRAM on the POWER7+ processor die is significant for
several reasons:
Latency improvement
A six-to-one latency improvement occurs by moving the L3 cache on-chip compared to L3
accesses on an external (on-ceramic) ASIC.
Bandwidth improvement
A 2x bandwidth improvement occurs with on-chip interconnect. Frequency and bus sizes
are increased to and from each core.
No off-chip driver or receivers
Removing drivers or receivers from the L3 access path lowers interface requirements,
conserves energy, and lowers latency.
Small physical footprint
The performance of eDRAM when implemented on-chip is similar to conventional SRAM
but requires far less physical space. IBM on-chip eDRAM uses only a third of the
components used in conventional SRAM, which has a minimum of six transistors to
implement a 1-bit memory cell.
Low energy consumption
The on-chip eDRAM uses only 20% of the standby power of SRAM.
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IBM Power 750 and 760 Technical Overview and Introduction
Core Core
L2 Cache L2 Cache
Fast local L3 Fast local L3
Cache Region
Cache Region
L3 Cache and Chip Interconnect
Fast local L3
Fast local L3
Cache Region
Cache Region
L2 Cache L2 Cache
Core Core
Core Core
L2 Cache L2 Cache
Fast local L3 Fast local L3
Cache Region
Cache Region
Fast local L3 Fast local L3
Cache Region Cache Region
L2 Cache L2 Cache
Core Core
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