IBM Power 750 Technical Overview And Introduction page 70

Figure 2-10 shows the memory location codes and how the memory riser cards are divided in
quads, each quad being attached to a memory buffer.
Quad A
Quad B
Figure 2-10 Memory Riser Card for Power 750 and Power 760 Systems
A POWER7+ DCM uses one memory controller from each processor core (MC0 and MC1)
with two channels from memory controller 0 (channels A and B) and two channels from
memory controller 1 (channels C and D) for a total of four memory channels per DCM. Two
channels are attached to one memory riser card, with one channel to each buffer chip. The
two remaining memory channels from the POWER7+ DCM module attach to the second
memory riser card. Four DDR3 DIMMs will attach to each buffer chip with a total of 16 per
DCM and a maximum of 64 per system.
Memory placement rules
The memory-placement rules are as follows:
Each DCM requires two memory riser cards.
Each riser card must be populated at least with one pair of DIMMs.
The DIMMs of a DIMM-pair as listed in the tables (Table 2-4 on page 57 through Table 2-7
on page 59), must have the same size.
Each DIMM within a DIMM quad area (C1, C2, C3, and C4 or C5, C6, C7, and C8) must
be identical, although memory DIMMs in C1, C2, C3, and C4 might be separate feature
codes than those used in C5, C6, C7, and C8. A quad does not have to filled before
putting another pair of DIMMs into another quad.
For optimal performance, memory should be evenly spread across the memory riser
cards.
FC EM4D (64 GB - 2 x 32 GB DIMMs) is available only in the Power 760 and not
supported in the Power 750.
Third-party memory: Although the system uses industry standard DIMMs, third-party
memory is not supported.
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IBM Power 750 and 760 Technical Overview and Introduction
Buffe r B
Memory Riser Card
Slot #1 – P3-Cn-C1
Slot #2 – P3-Cn-C2
Slot #3 – P3-Cn-C3
Slot #4 – P3-Cn-C4
Bu ffe r A
Slot #5 – P3-Cn-C5
Slot #6 – P3-Cn-C6
Slot #7 – P3-Cn-C7
Slot #8 – P3-Cn-C8