Overview; Processor Interconnects - IBM Power 750 Technical Overview And Introduction

2.2.1 Overview

Figure 2-6 illustrates the major components of the Power 750 and Power 760 CPU card.
Regulator #1
DCM0
DCM2
Regulator #2
Front
Regulator #3
DCM3
DCM1
Regulator #4
Figure 2-6 IBM Power 750 and Power 760 CPU board

2.2.2 Processor interconnects

This section describes the processor to memory architectural differences between IBM
POWER7 technology-based IBM Power 750 (8233-E8B) and the IBM POWER7+
technology-based Power 750 (8408-E8D) and Power 760 (9109-RMD) servers.
Historically new server models within a model family (such as Power 710) have carried
forward a similar, though enhanced, memory and I/O architecture of their previous model.
However, this case is not the same for POWER7+ Power 750 and Power 760. With these new
server models, changes to the bus architecture might require additional performance
considerations for partitions that need processor and memory resources that span multiple
processor sockets.
Similar to its previous POWER7 version, the POWER7+ technology-based Power 750 design
still provides 32 cores across four processor sockets, but the system design delivers a new
architecture. The Power 750 (8404-E8D) and Power 760 systems introduce a two-tier
interconnect architecture for a 4-socket system design. With this implementation, the socket
and node are logically the same. For the Power 770, the system enclosure and the node are
logically the same. For the Power 795, the book and node are logically the same. One tier is
for intra-node communication, and the second tier is for inter-node communication. This
two-tier interconnect enables more cores and greater throughput.
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IBM Power 750 and 760 Technical Overview and Introduction
Memory Riser #1
Memory Riser #2
Memory Riser #3
Memory Riser #4
Regulator #5 TPMD Slot
Memory Riser #5
Memory Riser #6
Memory Riser #7
Memory Riser #8
Midplane