Icom IC-706 Service Manual page 12

(1) REFERENCE LOOP PLL
The oscillated signal at the reference VCO (012, 013) is
amplified at the amplifiers (013, 016) and is then applied to
the DOS IC (IC10 pin 46). The signal is then divided and
detected on phase with the DDS generated frequency.
The detected signal output from ICl0 (pin 56) is converted
into a DC voltage (lock voltage) at the loop filter (R88,
R203, C132) and then fed back to the varactor diode (013)
in the VCO circuit.
3-3-3 2ND LO AND REFERENCE
OSCILLATOR CIRCUITS
The reference oscillator (Xl, 014) generates a 30.0 MHz
frequency used for the 2 DDS ICs as a system clock and for
the LO output. The oscillated signal is bUffer-amplified at
027, doub[ed by 2 at 015 and the 60 MHz frequency is
picked up at the bandpass filter (L37, l38). The 60 MHz
signal is applied to the IF unit as a 2nd LO signal.
(2) MAIN LOOP PLL
The oscillated signal at one of the main loop VCOs (06, 08)
is amplified at the buffer amplifiers (010, 036) and is then
applied to the PLL IC (IC13 pin 8). The signal is then
divided and detected on phase with the reference loop
output frequency.
The detected signal output from IC13 (pin 12) is converted
into a DC voltage (lock voltage) at the active loop filter
(047-049) and then fed back to one of the varactor diodes
(04, 06) in the VCO circuits. While operating on 60 MHz
and above, the VCO output is doubled by 2 at 08 and
amplified at 037.
3·3-4 BFO CIRCUIT
The DDS IC (IC12) generates a 10-bit digital signal. The
signal is converted to an analog wave signal at the
O/A
converter. The analog wave is passed through the high-
pass filter and low-pass filter. The 9 MHz BFO signal
passes through the bandpass filter and is then applied to
the MAIN unit via the "BFO" signal line.
While transmitting in RTTY mode, the RTTY keying signal is
applied to IC12 pin 3 to shift the generated frequency and to
obtain 2 frequencies for FSK operation.
The oscillated signal passes through a low-pass or band-
pass fitter and is then applied to the MAIN unit as a 1st LO
signal.
White receiving in FM or FM narrow mode, the BFO circuit
generates a 9.4665 MHz or 9.4650 MHz frequency as the
3rd LO signal, respectively.
Frequency construction
[ANTI] [ANT2]
0.03- 60-
60 MHz 200 MHz
MAIN unit
To
WFM detector
(IC9)
To AF selector
1------..
switch
AF signal
ToTX
FM PLLIC
(IC37)
To
FMIFIC
(IC18)
NN
:x::x:
22
11')0
CDII')
CD CD
"':"':
00>
FSKkeying
9.01 MHz
(BFO)
PLL unit
I
I
I
I
I
I
I L
_
60.00 MHz
10.6605-
10.683 MHz
69.0415-
269.Q115 MHz
015
Reference loop PLL
~ase
IC10
I
I
I
detector DDS
t--+
I
----. . . . . . . . - -------. . . . .
..I..
Ref.OSC
Xl
0
'V
30.00 MHz
T
014
69.0415-
129.0115 MHz
'V )------.---'
012
06.08
-
-
-
- - - -
-
--
-
- -
- - -
- -
-
- -
-
-,
'V )--_-.
...J
3-7