Receiver Circuits - Icom ID-RP2 Service Manual

SECTION 3

3-1 RECEIVER CIRCUITS

3-1-1 RF CIRCUIT (10 GHz MODULE)
The RF circuit amplifi es signals within the range of frequen-
cy coverage and fi lters out-of-band signals. And converts the
fi ltered signals to the fi xed frequency of the 1st IF signal.
The signals from the antenna are applied to [ANT] con-
nector (CHASSIS unit; W1) and then passed through the
duplexer unit (CHASSIS unit; FI1). The received signals from
the duplexer are amplifi ed at 2 RF amplifi ers in the 10 GHz
module and then passed through the bandpass filter. The
fi ltered signals are mixed with the 1st LO signal coming from
the RX VCO circuit in the 10 GHz module to produce the
1747.5 MHz 1st IF signal. The 1st IF signal passes through
the bandpass fi lter to suppress out-of-band signals.
The fi ltered signal is applied to the IF circuit (IF unit).
3-1-2 IF CIRCUITS (IF UNIT)
The IF circuit converts the 1st IF signal to the 2nd IF signal
with the PLL output frequency.
The 1st IF signal from the 10 GHz module is applied to the
level adjust section of the IF converter (IC404, pin 4) and
output from pin 61 (IC404). The level adjusted signal is
passed through the bandpass fi lter (FI402) and then applied
to the mixer section of the IF converter (IC404, pin 52). The
applied signal is mixed with the 2nd LO signal coming from
the RX 2nd VCO circuit (Q404, Q405, D402) via the doubler
circuit (Q406) to convert to a 374 MHz 2nd IF signal.
• RF AND IF CIRCUITS (RECEIVER)
10.000–10.025 GHz
10.015–10.175 GHz
DUPLEXER
IF UNIT
IC514
LVDS
ID-RP2C
IC
CIRCUIT DESCRIPTION
10 GHz MODULE
AMP
AMP
IC9
IC11
FPGA
A/D
IC
C - 3 - 1
The 2nd IF signal is output from pins 48 and 49 of the IF
converter (IC404) and then applied to the level adjust section
of the I/Q demodulator (IC401, pins 3, 4) via the bandpass
fi lter (FI403). The level adjusted signal is mixed with the 3rd
LO signal coming from the RX 3rd VCO circuit (Q401, Q402,
D401) at the demodulator section (IC401, pins 3, 4) to de-
modulate the I/Q signals.
The demodulated I/Q signals are output from pins 37 and 38
(IC401; for I signals), and pins 35 and 36 (IC401; for Q sig-
nals) and are applied to the A/D converter.
3-1-3 FPGA CIRCUIT (IF UNIT)
The demodulated I/Q signals from the I/Q demodulator
(IC401) are applied to the A/D converter (IC9, pins 2, 3 for
I signals, pins 10, 11 for Q signals) to convert to 5-bit digital
I/Q signals, and output from pins 40–44 (IC9; for I signals)
and pins 17–21 (IC9; for Q signals).
The digital I/Q signals are applied to the FM detector section
of the FPGA IC (IC11, pins 7–11 for I signals, pins 17–21
for Q signals) and output from pins 140–144 (IC11). The de-
tected signals are applied to the D/A converter (R121–R136)
and I/Q fi lter (L23–L28, C123, C125, C126, C128, C129) to
convert to analog FM demodulated signal.
The analog FM demodulated signal is applied to the clock
recovery circuit (IC15, IC17, IC21, IC523) to recover the
clock and data signals. The recovered clock and data sig-
nals are applied to the latch section of FPGA IC (IC11, pins
135, 136) and then output from pins 27 and 28. The RX
clock (RX_CLK) and RX data (RX_DAT) signals are applied
to the TX LVDS controller (IC514) to convert to differential
signal and then applied to the connected repeater controller
(ID-RP2C) via [DATA B] that is connected to J9.
1st LO:
8252.5–8427.5 MHz
BPF
1st mixer
IC401 FI403
I/Q DE-
BPF
MODULATOR
2nd IF:
374 MHz
1st IF:
1747.5 MHz
BPF
IC404
IF
CONVERTER
BPF
FI402