Power Supply Circuits - Icom ID-RP2 Service Manual

The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC404, pin
30) is passed through the loop filter and is then applied to
the RX 2nd VCO circuit.
3-3-3 RX 3RD PLL CIRCUIT (IF UNIT)
The RX 3rd PLL circuit oscillates the RX 3rd LO frequency
and the signal is applied to the 3rd mixer section in the I/Q
demodulator IC (IC401).
The oscillated signal from the RX 3rd VCO circuit (Q401,
Q402, D401) is amplifi ed at the buffer amplifi er (Q403) and
then applied to the 3rd mixer section of the I/Q demodulator
IC (IC401, pin 26).
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC401, pin
22) is passed through the loop filter and is then applied to
the RX 3rd VCO circuit.
3-3-4 TX 3RD PLL CIRCUIT (IF UNIT)
The 3rd PLL circuit oscillates the TX 3rd LO frequency
and the signal is applied to the 3rd mixer section in the I/Q
modulator (IC201).
The oscillated signal from the TX 3rd VCO circuit (Q201,
Q202, D201) is applied to the tripler circuit (Q203) and then
applied to the 3rd mixer section of the I/Q modulator (IC201,
pin 26).
• PLL CIRCUITS
I/Q signals from
FPGA circuit
CPU
IC509
X204
25 MHz
I/Q signals to
FPGA circuit
PLL
IC201
×3
TX 3rd
LOOP
VCO
350.5 MHz
748 MHz
RX 3rd
LOOP
VCO
IC401
PLL
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC201, pin
22) is passed through the loop filter and is then applied to
the TX 3rd VCO circuit.
3-3-5 TX 2ND PLL CIRCUIT (IF UNIT)
The 2nd PLL circuit oscillates the TX 2nd LO frequency
and the signal is applied to the 2nd mixer section in the IF
converter (IC204).
The oscillated signal from the TX 2nd VCO circuit (Q204,
Q205, D204) is applied to the tripler circuit (Q206) and then
applied to the 2nd mixer section of IF converter (IC204, pin
40).
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC204, pin
30) is passed through the loop filter and is then applied to
the TX 2nd VCO circuit.

3-4 POWER SUPPLY CIRCUITS

Line
Common 5 V controlled by the +5 V regulator
5 V circuit (IC1). The output voltage is applied to
the baseband clock circuit (Q1, X1), etc.
Common 3.3 V converted from the 5V line
by the 3.3 V regulator circuit (IC12). The output
3.3 V
voltage is applied to the FPGA IC (IC11) and
A/D converter (IC9), etc.
Common 2.5 V converted from the 5V line
2.5 V by the 2.5 V regulator circuit (IC13). The output
voltage is applied to the FPGA IC (IC11), etc.
FI202
BPF
PLL
×2
TX 2nd
LOOP
VCO
602.25 MHz
686.75 MHz
RX 2nd
LOOP
VCO
×2
PLL
BPF
FI402
C - 3 - 3
Description
1st IF signal to
the 10 GHz module
IC204
IC404
1st IF signal from
the 10 GHz module