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SDM-309B Satellite Modem
2.2 V.35 Interface
2.2.1 Functional Description
The V.35 digital interface (Figure C-11) provides level translation, buffering and
termination between the internal modem signals and the V.35 DCE interface on the rear
panel. Electrical characteristics of the interface signals are defined in CCITT
Recommendation V.35. The electrical and mechanical specifications are summarized in
Sections 2.2.2 and 2.2.3. A functional block diagram of the interface is shown in Figure
C-12.
The V.35 interface provides a Serial Clock Transmit (SCT) clock signal at the modem
data rate. In the INTERNAL clock mode, the data to be transmitted, Send Data (SD)
must be synchronized to SCT. In the EXTERNAL clock mode, clock is accepted on the
Serial Clock Transmit External (SCTE) input to clock in the data to be transmitted. In
either case, the phase relationship between the clock and data is not important as long as
it meets the jitter specification because a clock phase correction circuit is provided which
shifts the clock away from the data transition times. The clock selection is jumper
selectable at JP1 on the front edge of the board. When there is no jitter on the clock
source, the AUTO setting is used. The NORMAL setting is used when standard
specifications on clock and data relationships exist. The INVERT mode is used when the
incoming clock is inverted from the standard clock and data relationship.
Data received by the modem is output on the Received Data (RD) lines while the
recovered clock is output on the Serial Clock Receive (SCR) lines. For applications that
require the rising edge of the clock to occur in the middle of the data bit time, Receive
Clock NORMAL mode should be selected. INVERT mode puts the falling edge of SCR
in the middle of the data bit. This selection can be made from the front panel in the
configuration menu.
The Request to Send (RTS) lines are jumpered to the Clear to Send (CTS) lines, since
the modem does not support polled operation. Data Set Ready (DSR) indicates that the
modem is powered up. Receive Line Signal Detect (RLSD) indicates that an RF carrier is
being received and demodulated with a sufficiently low error rate for the decoder to
remain locked.
The V.35 interface also provides bi-directional relay loopback of both the clock and data
at the DCE interface. In LOOPBACK, from the DTE side, SD is connected to RD, and
either SCT or SCTE (in INTERNAL or EXTERNAL mode) is looped back to SCR.
From the modem side, the received data and recovered clock are routed back to the
modulator input for retransmission.
Loop timing is supported by the selection of jumper JP10 on the front edge of the card.
When in the ON position the internal clock (SCT) is replaced by the clock recovered
from the receive (IF) data (RD). Active loop timing is indicated by a yellow light on the
MN/U-SDM309B Rev. #
External Channel Unit
C-C–17
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